Obviousness

To analyze the obviousness of US Patent 11307995 under 35 U.S.C. § 103, we must identify prior art references, their disclosures, and the motivation a person having ordinary skill in the art (PHOSITA) would have had to combine them to arrive at the claimed invention.

The priority date for US11307995 is September 9, 2014. Therefore, any references filed or published before this date are considered prior art. From the "PRIORITY/INCORPORATION BY REFERENCE" section of US11307995, the relevant prior art documents explicitly mentioned and incorporated by reference are:

• U.S. Patent Publication 2014/0215129, for "Cooperative Flash Memory Control" (published July 31, 2014).
• U.S. Utility patent application Ser. No. 14/047,193, filed on October 7, 2013, for "Multi-Array Operation Support And Related Devices, Systems And Software."

Obviousness Analysis: US11307995 in view of US2014/0215129 and US14/047,193 (or general knowledge)

The independent claims (Claims 1, 13, and 14) of US11307995 describe a system and method where a memory controller subdivides a Logical Block Address (LBA) into discrete address fields corresponding to hierarchical physical elements (e.g., channels, dies, erase units, pages). At least one of these fields is a virtual address, which the memory controller translates to a physical address. Crucially, this translation ensures the virtual address resolves within the physical bounds of a larger, hierarchically superior structure, allowing it to be freely mapped to any constituent physical element within that structure to mask defects and perform maintenance, without the host losing coherence with the hierarchical boundaries.

1. Disclosures of the Primary Prior Art References:

A. U.S. Patent Publication 2014/0215129 ("Cooperative Flash Memory Control")
This publication discloses a "cooperative management mode" where a flash memory controller exposes the underlying physical flash geometry to a host system. The host then requests this geometry description ("geometry export") and defines an address assignment where the host's linear LBA range maps directly onto the physical block addresses (PBAs) of the flash storage. In this mode, the memory controller gathers statistics for flash maintenance and notifies the host when maintenance is required. For example, a defective and unavailable erase unit is reported to the host by the memory controller and noted within the LBA-to-PBA address map.

The US11307995 patent explicitly describes the limitations of this "cooperative management mode": "the host is burdened with numerous complex and hardware-specific media management tasks, including discovery and avoidance of failed structural elements (especially erase units and dies), leveling otherwise disparate wear between different erase units ('wear leveling'), reducing storage fragmentation ('garbage collection')... Thus design and implementation of a host system needed to interact with and manage the flash memory in physical access mode can become tremendously complex and, making matters worse, may require substantial and expensive re-design as new generations of flash memory devices become available."

B. U.S. Utility patent application Ser. No. 14/047,193 ("Multi-Array Operation Support And Related Devices, Systems And Software")
While the full content of US14/047,193 is not provided here, its title suggests it addresses multi-array operations and related support, which would inherently involve managing multiple physical memory elements and potentially hierarchical memory organization. It is generally known in the art of flash memory systems that memory controllers manage physical resources using various addressing schemes, including subdividing addresses and employing techniques for wear leveling and bad block management, often involving some form of address translation. The description of US11307995 also refers to a general concept where "a memory controller that subdivides an incoming memory address into multiple discrete address fields corresponding to respective hierarchical groups of structural elements within a target nonvolatile semiconductor memory system..." This general concept, especially concerning hierarchical memory structures like channels, dies, erase units, and pages, would be well-understood by a PHOSITA prior to 2014.

2. Motivation to Combine and Explanation of Obviousness:

A person having ordinary skill in the art (PHOSITA) would have been motivated to combine the teachings of US2014/0215129 with hierarchical addressing and memory management techniques known in the art (e.g., from US14/047,193 or common knowledge) for the following reasons:

Motivation:
The explicit problem identified in US11307995 regarding the "cooperative management mode" of US2014/0215129 is the significant burden placed on the host for flash media management. The host must be "fully aware of the underlying flash device geometry" and "is burdened with numerous complex and hardware-specific media management tasks, including discovery and avoidance of failed structural elements..., leveling otherwise disparate wear..., reducing storage fragmentation..., and refreshing... data nearing its retention time limit..." This complexity leads to "substantial and expensive re-design as new generations of flash memory devices become available."

A PHOSITA would naturally seek to reduce this host burden while retaining the performance advantages (e.g., predictable I/O latency) of exposing some aspects of the physical geometry, as opposed to the unpredictable latency of a fully virtualized Flash Translation Layer (FTL) approach.

Combination and Claim Elements:

• Memory Controller, LBA Subdivision, Hierarchical Elements: US2014/0215129 already involves a memory controller in a flash memory system that handles LBAs in relation to hierarchical physical elements. US14/047,193 (or general knowledge) would further reinforce the concept of subdividing logical addresses into fields corresponding to channels, dies, erase units, and pages within a flash memory system.

• Virtual Address Field and Translation: To alleviate the host's burden of managing individual defects (like defective erase unit 'B' reported in US2014/0215129), a PHOSITA would consider having the memory controller take on localized virtualization. This involves treating at least one of the subdivided address fields (e.g., the erase unit address field) as a virtual address. Address translation is a well-established technique in memory management for handling bad blocks and wear leveling.

• Localized Virtualization within Hierarchical Bounds: The inventive step of US11307995 is performing this virtualization such that the virtual address "is ensured to resolve to an element within the physical bounds of a larger (hierarchically-superior) structure, but may be freely mapped to any of the constituent physical elements of that larger structure." Faced with the problem of host burden, a PHOSITA would observe that while exposing high-level physical structures (like dies or channels) offers performance benefits, abstracting away lower-level defects (like individual bad erase units) could significantly reduce host complexity. This would lead the PHOSITA to virtualize resources like erase units within the confines of a die (the hierarchically superior structure in this context). The US11307995 itself describes the "hierarchically virtualized mode" as where "the memory controller maps the LBAs discontiguously, skipping over reserved and defective erase units, and thus virtualizing the pool of erase units within each individual flash die while maintaining the physical boundary between dies as reported to the host." This is presented as an improvement over the cooperative mode, directly addressing its shortcomings.

• Free Mapping for Defect Masking and Maintenance: By virtualizing at a localized hierarchical level (e.g., erase units within a die), the memory controller gains the freedom to remap a virtual erase unit address to any available physical erase unit within that same die. This enables the controller to transparently mask defective structural elements and swap operational elements (e.g., spare erase units for worn-out ones) in and out of service for maintenance (wear leveling, garbage collection, scrubbing) without needing host intervention for every such event.

• Maintaining Host Coherence: The crucial aspect of maintaining "coherence with respect to boundaries between hierarchical structures" is a direct result of performing this virtualization locally (e.g., within a die, but not across dies or channels). This approach is explicitly designed to avoid the performance degradation and unpredictable latency associated with a full FTL that completely obscures the underlying physical hierarchy from the host.

Conclusion:
A PHOSITA, seeking to overcome the challenges of host burden and complexity inherent in the "cooperative management mode" disclosed by US2014/0215129, would have found it obvious to implement localized hierarchical address virtualization. By combining the problem statement of US2014/0215129 (host burden with defect management) with the general knowledge of hierarchical memory organization and address translation (e.g., from US14/047,193) for managing defects and wear, the PHOSITA would be motivated to have the memory controller perform virtualization at a specific hierarchical level (e.g., erase units within a die). This combination would enable transparent defect masking and maintenance while preserving the host's perception of higher-level hierarchical boundaries and avoiding the drawbacks of a full FTL, thereby arriving at the claimed invention of US11307995.