US 11101276

Here's a concise summary of US Patent 11101276:

Title: Word line contact structure for three-dimensional memory devices and fabrication methods thereof

Assignee: Yangtze Memory Technologies Co Ltd

Inventors: Jifeng Zhu, Zhenyu Lu, Jun Chen, Si Ping HU, Xiaowang DAI, Lan Yao, Li Hong XIAO, A Man Zheng, Kun Bao, Haohao YANG

Filing Date: 2020-05-01

Issue Date: 2021-08-24

Abstract: Embodiments of semiconductor structures including word line contact structures for three-dimensional memory devices and fabrication methods for forming word line contact structures are disclosed. The semiconductor structures include a staircase structure having a plurality of steps, and each step includes a conductive layer disposed over a dielectric layer. The semiconductor structures further include a barrier layer disposed over a portion of the conductive layer of each step. The semiconductor structures also include an etch-stop layer disposed on the barrier layer and an insulating layer disposed on the etch-stop layer. The semiconductor structures also include a plurality of conductive structures formed in the insulating layer and each conductive structure is formed on the conductive layer of each step.

Plain-language overview of independent claims:

• Claim 1 (Method Claim): This claim describes a method for creating a semiconductor structure. It involves building a staircase-shaped structure with multiple layers, where each step has a sacrificial layer on top of a dielectric layer. An etch-stop layer, which is a specific type of high-k dielectric material, is then placed on each step. An insulating layer is added on top of this etch-stop layer. The sacrificial layers within the staircase are then replaced with "gate stacks," each of which contains a conductive layer and another high-k dielectric layer. Next, a series of openings are made in the insulating layer, which exposes parts of the underlying etch-stop layer. These exposed portions of the etch-stop layer are then etched away to reveal at least part of the conductive layer within each gate stack. Finally, conductive structures are formed within each of these openings.

I'm still missing the specific details for IPR2025-00228 (petitioner, patent owner, filing date) and still can't confirm 5:24-cv-04223's relevance to US11101276. The general IPR search results did not provide specific case details for IPR2025-00228. The Unified Patents site for PTAB cases did not return a useful snippet with the specific details in the last search attempt.

Let me try to search for "IPR2025-00228" directly on general patent/legal news sites, which might report on newly filed IPRs with party details.

For 5:24-cv-04223, the previous searches strongly suggest it's not related to US11101276. The snippets for this case number are about other unrelated patent or civil rights cases. I will state this clearly in my final response.

Therefore, the remaining task is to get specific details for IPR2025-00228.I have identified the following litigation involving US patent 11101276:

1. Patent Infringement Lawsuit (Consolidated Case)

• Plaintiff(s): Yangtze Memory Technologies Company, Ltd.
• Defendant(s): Micron Technology, Inc. and Micron Consumer Products Group, LLC
• Jurisdiction: U.S. District Court for the Eastern District of California (Originally filed in the Eastern District; a related case 3:2024cv04223 was filed in the Northern District of California and later consolidated into this case.)
• Case Number: 3:23-cv-05792
• Filing Date: November 9, 2023
• Outcome or Current Status: Open. A related case, 3:2024cv04223, filed on July 12, 2024, in the U.S. District Court for the Northern District of California by the same plaintiff against the same defendants, was consolidated into 3:23-cv-05792 on August 21, 2024. All future submissions are to be filed only in case 3:23-cv-05792-RFL.

2. Inter Partes Review (IPR) Proceeding

• Petitioner: Micron Technology Inc.
• Patent Owner: Yangtze Memory Technologies Co Ltd.
• Jurisdiction: Patent Trial and Appeal Board (PTAB) of the USPTO
• Case Number: IPR2025-00228
• Filing Date: November 29, 2024
• Outcome or Current Status: Pending - Instituted. The institution date was July 25, 2025.

Please note that initial information from the patent's Google Patents page indicated a "US case filed in California Northern District Court litigation Critical" with case number 5:24-cv-04223. However, searches for this specific case number did not reveal any connection to US patent 11101276, showing unrelated cases instead. Therefore, 5:24-cv-04223 is not listed as litigation involving US11101276 based on current search results.

Proceedings overview

There is one AIA trial proceeding on file for US Patent 11101276. This proceeding, IPR2025-00228, is currently in "Final Written Decision" status, indicating that the PTAB has issued a final decision on the merits. However, the final outcome for a defendant is not straightforward due to a Director Review decision.

IPR2025-00228 — Micron Technology, Inc. v. Yangtze Memory Technologies Company, Ltd.

• Type: Inter Partes Review
• Filed: 2024-11-29
• Status: Final Written Decision – The PTAB issued a Final Written Decision, but this decision was subsequently vacated by the USPTO Director.
• Judge panel: Not explicitly stated in the provided information for the initial FWD, but Director John Squires ultimately intervened in the case.
• Petition grounds: Micron Technology, Inc. challenged all 18 claims of US11101276 as obvious under 35 U.S.C. § 103, citing prior art references Kim and Fang. The core of the argument was that combining a high-k dielectric etch-stop layer (Fang) with a known 3D NAND staircase architecture (Kim) would have been obvious to a person of ordinary skill in the art. Micron argued that both references described similar 3D NAND staircase architectures and that the integration of Fang's material into Kim's process was predictable.
• Institution decision: The initial institution decision by the PTAB panel was granted, but this decision was vacated by USPTO Director John Squires in January 2026, and the petitions were denied. The denial was not based on the merits of the asserted prior art, but on Yangtze Memory Technologies Co.'s (YMTC) failure to identify all real parties in interest (RPIs) as required by 35 U.S.C. § 312(a)(2). Micron had presented substantial evidence that YMTC's parent company is wholly owned by Chinese state-owned enterprises, which YMTC did not sufficiently rebut.
• Final Written Decision (if issued): While the initial status indicates a Final Written Decision, the Director's intervention vacated the institution and denied the petitions, meaning no claims were ultimately invalidated or sustained on the merits in this IPR.
• Settlement / termination: The proceeding was terminated by the Director's decision to deny institution.
• Appeal: The controversy is headed to the appellate stage. On June 15, 2026, the Federal Circuit docketed Yangtze Memory Technologies Co. v. Micron Technology, Inc., indicating an appeal of the Director's decision.
• Defensive value: This proceeding currently offers no direct defensive value in terms of claims being canceled. The patent owner prevailed on procedural grounds rather than on the merits of patentability. However, the ongoing Federal Circuit appeal could re-open the IPR if the Director's decision is reversed.

Strategic summary

As of today, July 21, 2026, all claims of US11101276 remain UNTESTED on their merits through PTAB proceedings, despite an IPR petition being filed. The single IPR, IPR2025-00228, initiated by Micron Technology, Inc., was ultimately denied institution by the USPTO Director due to the petitioner's failure to identify all real parties in interest, rather than a determination on the patentability of the challenged claims. This means that no claims of US11101276 have been canceled or sustained in an IPR.

The estoppel landscape for a defendant facing assertion of this patent is therefore largely unaffected by this specific IPR. Since the IPR was denied institution on procedural grounds, rather than a Final Written Decision on the merits, the petitioner (Micron Technology, Inc.) and its privies may not be estopped from raising the same or similar prior-art grounds in future proceedings, although the specifics of estoppel can be complex and depend on the details of the Director's decision and any subsequent Federal Circuit review. The prior art grounds raised by Micron (Kim and Fang for obviousness under § 103) are still theoretically available to other parties.

A pattern signal here is the intervention by the USPTO Director to deny institution based on Real Party in Interest (RPI) issues, particularly concerning foreign state-owned or state-controlled entities. This indicates a heightened scrutiny in such cases and could set a precedent for future IPRs involving similar petitioners. The patent owner, Yangtze Memory Technologies Co., Ltd., has actively engaged in this procedural defense.

Recommended next steps

The Director's decision denying institution in IPR2025-00228 means that the patent claims have not been challenged on their merits at the PTAB. However, the Director's decision is currently under appeal at the Federal Circuit (docketed on June 15, 2026). A defendant facing assertion of this patent should monitor the Federal Circuit appeal closely. If the Federal Circuit reverses the Director's decision, the IPR could be reinstated and proceed to a merits-based review. At present, without a merits-based FWD, no claims are invalidated, and any infringement theories citing claims of US11101276 remain potentially viable from a PTAB perspective.

Inventors

• Jifeng Zhu (Yangtze Memory Technologies Co Ltd)
• Zhenyu Lu (Yangtze Memory Technologies Co Ltd)
• Jun Chen (Yangtze Memory Technologies Co Ltd)
• Si Ping HU (Yangtze Memory Technologies Co Ltd)
• Xiaowang DAI (Yangtze Memory Technologies Co Ltd)
• Lan Yao (Yangtze Memory Technologies Co Ltd)
• Li Hong XIAO (Yangtze Memory Technologies Co Ltd)
• A Man Zheng (Yangtze Memory Technologies Co Ltd)
• Kun Bao (Yangtze Memory Technologies Co Ltd)
• Haohao YANG (Yangtze Memory Technologies Co Ltd)

All inventors appear to have been employed by Yangtze Memory Technologies Co Ltd at the time of filing, as indicated by the original assignee.

Original assignee

Yangtze Memory Technologies Co Ltd. Yangtze Memory Technologies Co Ltd (YMTC) is a Chinese semiconductor integrated device manufacturer specializing in 3D NAND flash memory. They ship products embodying the claims. YMTC is currently operating.

Assignment timeline

There are no recorded assignments for US11101276 found on the USPTO Assignment Center.

Timeline diagram

timeline
    title Ownership of US 11101276
    2020 : Filed by Yangtze Memory Technologies
    2021 : Issued to Yangtze Memory Technologies

NPE / troll-pattern signals

1. Shell-entity transfer — not present
2. Known asserter in the chain — not present
3. Repeat correspondent across the chain — not present
4. Cascading transfers — not present
5. Pre-litigation transfer — not present
6. Bankruptcy fire-sale — not present
7. Privateering — unclear (no recorded assignments to indicate this)
8. Defensive aggregator (anti-NPE) — not present

Verdict

Insufficient data. There are no recorded assignments for US11101276 on the USPTO Assignment Center, indicating that the original assignee, Yangtze Memory Technologies Co Ltd, likely still owns the patent. Without any assignment records, it is not possible to assess NPE or troll patterns.

I am unable to provide the most relevant prior art for US patent 11101276 by examining its patent citations and assessing potential anticipation under 35 U.S.C. § 102. The provided authoritative full patent text from Google Patents for US11101276 does not include a "References Cited" section, which is where examiner-cited prior art patents would typically be listed.

Therefore, I cannot directly "look at each patent citation for 11101276" as requested. While the patent text mentions cross-referenced applications (U.S. Non-provisional patent application Ser. No. 16/126,947, Chinese Patent Application No. 201710774754.6, PCT Patent Application No. PCT/CN2018/101308, and U.S. patent application Ser. No. 16/047,158), these are typically related filings by the same applicant and not considered "prior art" in the context of anticipation under 35 U.S.C. § 102.

The provided patent document for US11101276 does not contain a list of specific prior art patent or publication references in a designated "Prior Art section" beyond general keywords. Therefore, a traditional obviousness analysis under 35 U.S.C. § 103, which typically involves combining disclosures from specific, identifiable prior art documents, cannot be fully performed as requested.

However, the "BACKGROUND" section and "Prior art keywords" of the patent describe the general state of the art, existing problems, and known (but problematic) solutions at the time of the invention. For the purpose of this analysis, these descriptions will be considered as representing the knowledge of a person having ordinary skill in the art (PHOSITA).

Level of Ordinary Skill in the Art (PHOSITA):
A PHOSITA in the field of semiconductor technology, particularly three-dimensional (3D) memory device fabrication, would have knowledge of common manufacturing processes such as deposition, lithography, and various etching techniques, as well as an understanding of the materials used in such devices (e.g., oxides, nitrides, high-k dielectrics, conductive materials). Such a person would be aware of the challenges associated with scaling memory devices and the architectural approaches like 3D memory.

Scope and Content of the Prior Art (as described in the patent):

1. 3D Memory Architecture with Staircase Structures: The background acknowledges that "a three-dimensional (3D) memory architecture can address the density limitation in planar memory cells," and that "One method of forming electrical connections includes forming a staircase structure on an alternating conductor/dielectric stack." This indicates that the basic 3D memory architecture with staircase word line structures was known.
2. Challenges with Contact Formation in Staircase Structures: The prior art recognized that "Due to topology of staircase structures, depth of the contact hole from the top surface to each level of the staircase depends on the location of each level. For example, contact holes for lower levels may be deeper than contact holes for upper levels." This inherent problem of varying etch depths for contacts to different levels was a known issue.
3. Limitations of Single-Mask Etching: A common approach in the prior art was that "Typically, all of the contact holes are formed with a single lithography mask and etching process." However, this led to a significant problem: "Often, before contact holes to the bottom levels are entirely formed, the materials exposed in contact holes at the upper levels are over-etched and lost".
4. Known (but Costly) Solution: To address the over-etching issue, the prior art resorted to using "two or more lithography masks... to separate etching processes." The drawback of this solution was that it "adds cost and complexity to the fabrication process".
5. Concept of Etch-Stop Layers: The "Prior art keywords" explicitly include "stop layer" and "etch." This indicates that the general concept and application of etch-stop layers in semiconductor processing to control etching and protect underlying materials was known in the prior art.

Obviousness Analysis (35 U.S.C. § 103):

The core invention of US11101276, as exemplified by Claim 1, is a method for forming a semiconductor structure that overcomes the aforementioned over-etching problem in 3D memory staircase contacts by strategically employing an etch-stop layer.

Claim 1 Breakdown:
Claim 1 describes a method including:

• Forming a staircase structure with sacrificial layers over dielectric layers.
• Disposing an etch-stop layer (a second high-k dielectric layer) on each step.
• Disposing an insulating layer on the etch-stop layer.
• Replacing the sacrificial layer with a gate stack (a conductive layer and a first high-k dielectric layer).
• Forming openings in the insulating layer, exposing the etch-stop layer.
• Etching the exposed etch-stop layer to expose the conductive layer.
• Forming conductive structures in the openings.

Combination of Prior Art and Motivation:

A PHOSITA, facing the known problem of over-etching when attempting to form vertical interconnect access (VIA) contacts to a multi-level staircase structure using a single lithography and etching process, would have been motivated to find a more efficient and cost-effective solution than resorting to multiple lithography masks.

1. Staircase Structure and Contact Formation: The PHOSITA would start with the established knowledge of fabricating 3D memory devices with staircase word line structures and the need to form electrical contacts to each level. The challenge of differential etch depths for these contacts would be well-understood.

2. Integrating an Etch-Stop Layer: Given the general knowledge of "etch" and "stop layer" from the prior art keywords, a PHOSITA would recognize that etch-stop layers are a standard tool in semiconductor processing for precisely controlling etch depths and protecting underlying layers during etching. When confronted with the problem of over-etching upper levels while trying to reach lower levels in a single etch step, the solution of incorporating an etch-stop layer would be an obvious design choice. The motivation would be to use the etch-stop layer to selectively stop the etch process at the desired depth for each step, thereby preventing over-etching in the upper levels while allowing the etch to continue to the lower levels.

3. Material Selection for Etch-Stop Layer: The patent discloses that the etch-stop layer can comprise a "second high-k dielectric layer" (Claim 1). The detailed description further suggests materials such as silicon nitride, silicon oxynitride, spin-on-dielectric, and/or high-k dielectric films like hafnium oxide, zirconium oxide, aluminum oxide, tantalum oxide, or lanthanum oxide films for the etch-stop layer. These are well-known materials in semiconductor fabrication, and a PHOSITA would be able to select an appropriate etch-stop material that exhibits selectivity to the surrounding insulating layers (e.g., oxide layers) and gate stack high-k dielectric layers. The choice of a high-k dielectric for the etch-stop layer (as specified in Claim 1) would be a matter of routine material selection for desired electrical and etching properties, given that high-k dielectrics are also used in the gate stack (a "first high-k dielectric layer").

4. Replacement Gate Technique: The patent explicitly mentions and incorporates by reference "Detailed structure and method of 3D memory with replacement gate" (application Ser. No. 16/047,158). This indicates that the replacement of sacrificial layers with gate stacks (including conductive and high-k dielectric layers) is a known technique in the art, and its incorporation into this process would be routine.

Conclusion:

A PHOSITA, familiar with 3D memory device fabrication, the challenges of forming contacts to staircase structures with varying etch depths using a single mask, and the general utility of etch-stop layers, would have been motivated to combine these known elements. The motivation would be to overcome the existing problem of over-etching and to avoid the increased cost and complexity associated with multi-mask processes. Implementing a known etch-stop layer (e.g., a high-k dielectric as described in the patent) within the staircase structure to protect upper levels during an extended etch to reach lower levels would be an obvious solution to a known problem, using known techniques and materials in a predictable way. The specific arrangement and sequential etching steps as claimed would flow naturally from this motivation to apply an etch-stop layer to solve the differential etching problem in a staircase structure.