Obviousness

Obviousness Analysis under 35 U.S.C. § 103 for US Patent 11018678

This analysis considers the obviousness of US Patent 11018678 by combining elements from the prior art references and background information explicitly disclosed within the patent text itself. The patent identifies a significant technological problem: the latency introduced by conventional clock domain crossing (CDC) circuits used to synchronize receiver and transmitter clock signals within a Field Programmable Gate Array (FPGA). [Definitions: One technological problem with FPGAs is that there is a need to synchronize receiving side and transmitting side clock signals within the FPGA.; Description, Conventional FPGA: a significant drawback of the clock domain crossing circuit 112 is that it adds latency... such that it slows the effective processing speed of FPGA 100.] The stated objective of the invention is to address this challenge without introducing unnecessary processing delay. [Definitions: An object of the present invention is to address technological challenges that currently exist in phase matching receiver side and transmitter side clocks of a FPGA without introducing unnecessary delay in processing.]

Prior Art References Disclosed in the Patent:

The patent explicitly describes or references the following as prior art or common general knowledge:

1. Conventional Field Programmable Gate Array (FPGA) Architecture (FIGS. 1, 1A, 1B, 1C): This includes:
   • FPGA Core 106 and FPGA Transceiver Banks 102. [Description, Conventional FPGA: FIG. 1 illustrates an exemplary schematic of a FPGA 100.]
   • Deserializer 104 and Serializer 110 (SERDES circuits). [Description, Conventional FPGA: An exemplary transceiver (including deserializer 104′ and serializer 110′) suitable for use in FPGA 100 is shown in FIG. 1A.]
   • Transceiver PLL 108 used by the serializer to generate a fast clock from a reference clock. [Description, Conventional FPGA: the serializer 110 (e.g., the transmitter) typically runs off a fast clock generated... by the transceiver phase-locked loop 108 within the transceiver bank 102 from a reference clock signal received by oscillator or clock generator 122.]
   • Receiver clock (RXCLOCK) generated by a clock and data recovery (CDR) circuit from the incoming data stream, and a transmitter clock (TXCLOCK) generated by the transceiver PLL. [Description, Conventional FPGA: the receiver clock domain is typically generated by a clock and data recovery (CDR) circuit from the incoming data stream. The transmitter clock is typically generated by the transceiver phase-locked loop 108.]
   • The use of Clock Domain Crossing (CDC) circuits 112 (e.g., asynchronous FIFO, asynchronous gearbox, mesochronous clock crossing circuit) for phase matching or synchronizing these different clock domains. [Description, Conventional FPGA: phase matching or synchronizing is provided using the clock domain crossing circuit 112 that adjusts the phases of the two clock domains. The clock domain crossing circuit 112 may be an asynchronous FIFO or an asynchronous gearbox, to name a few.]
   • The patent explicitly states the "significant drawback" of CDC circuits: "it adds latency related to the phase difference between the clocks plus the latency of the synchronizers used, and does not perform any computation, such that it slows the effective processing speed of FPGA 100." [Description, Conventional FPGA].
2. Synchronous Ethernet Systems: These systems were designed for synchronizing a transmitter to a receiver. However, the patent explicitly notes their inadequacy for the present invention's problem: "phase alignment in synchronous Ethernet is not necessary, synchronous Ethernet FPGA systems usually do not phase-align the receiver and transmitter sides of a link." [Definitions]. Furthermore, their internal PLLs are "configured to measure accurately only the frequency but does not have to measure the phase of the two clocks accurately." [Definitions].
3. General Electronic Components and Techniques:
   • Phase-Locked Loops (PLLs) and adjustable oscillators (voltage-controlled oscillators (VCOs), numerically/digitally-controlled oscillators (DCOs), ring oscillators, varactor-tuned oscillators, digital delay lines, voltage-controlled delay elements). Specific commercial examples are mentioned (e.g., Si550 from Silicon Labs, SY89295U from Micrel, HMC910 from Analog Devices). [Description, FIG. 4A: The adjustable oscillator 4200 may be implemented in a variety of ways...Other types of oscillators may be used including negative-resistance oscillators, Clapp oscillators, Colpitts oscillators, ring oscillators, and varactor-tuned oscillators, to name a few.]
   • Phase Detectors (PDs) for measuring phase differences (e.g., illustrated in FIGS. 8A-8D). [Description, FIGS. 8A-C are exemplary block diagram of a phase detector suitable for use in the field programmable gate array systems of FIGS. 3A-3F, 4A-4C and 5A-5F in accordance with an exemplary embodiment of the present invention.]
   • Control loops, controllers, and loop filters (e.g., first, second, third, fourth order filters with derivative components). [Description, FIG. 3A: Any loop filter order may be used in the controller 3202... a second-order loop filter may be used... a third-order filter may be used... a first-order filter is also an option...]
   • Zero-Delay Buffer (ZDB) PLLs (e.g., 4208a, 4208b). [Description, FIG. 4A: The FPGA 4100 includes zero-delay buffer PLLS 4208a, 4208b.]
   • High-frequency trading (HFT) as an application where rapid FPGA processing is desired. [Definitions: FPGAs are used in the financial industry in high frequency trading where the rapid processing of the FPGA is desired.]

A Person Having Ordinary Skill in the Art (POSITA) in FPGA design would be familiar with these conventional architectures, the inherent latency issues of CDC circuits, and the fundamental operation of PLLs, phase detectors, and control systems for clock synchronization.

Obviousness Analysis of Representative Claims:

Claim 1: Field Programmable Gate Array System (Internal PLL)

• Claimed Elements (Summary): An FPGA system with internal deserializer and serializer, computational circuitry, an internal phase detector comparing receiver-side and transmitter-side clock signals, and an internal phase controller that provides adjustment information to an internal adjustable PLL to adjust the phase of the serializer's clock.
• Prior Art Baseline: The conventional FPGA (FIG. 1, 1A, 1B) teaches an FPGA with deserializers (104) and serializers (110) operating with different clock domains, and the use of a transceiver PLL (108) to generate the serializer's fast clock. Crucially, it also teaches the problematic use of a CDC circuit (112) to synchronize these domains, with the explicit drawback of added latency. [Description, Conventional FPGA: a significant drawback of the clock domain crossing circuit 112 is that it adds latency...].
• Differences from Prior Art Baseline: The core difference is the replacement of the latency-inducing CDC circuit with an active feedback loop internal to the FPGA that precisely aligns the phases of the RXCLOCK and TXCLOCK using an internal phase detector, controller, and an adjustable PLL.
• Motivation to Combine: A POSITA, recognizing the explicit and significant latency drawback of CDC circuits in conventional FPGAs as highlighted by the patent, would be strongly motivated to find a solution that reduces or eliminates this latency. PLLs are a well-known means for clock synchronization and phase locking. The conventional FPGA already incorporates a transceiver PLL (108) for the serializer. Integrating an internal phase detector (as generically illustrated in FIGS. 8A-8D, which the patent describes as "suitable for use in the field programmable gate array systems") to compare the RXCLOCK and TXCLOCK, and an internal phase controller to feed adjustment information to an adjustable internal PLL (e.g., an adjustable transceiver PLL 3108 or a PLL with phase adjustment 3300 located within the FPGA core, as shown in FIG. 3A/3B), would be an obvious approach to actively align the phases and thereby avoid the latency of CDC circuits. The patent itself suggests that "PLL with phase adjustment 3300 may be located inside the FPGA 3100 fabric with adjustable feedback dividers, which in turn adjust the frequency of the PLL" or "may comprise a phase adjuster on the output of the loop, which adjusts the phase of the PLL directly." [Description, FIG. 3A]. This direct teaching, along with the explicit problem statement, makes the combination obvious. The synchronous Ethernet systems, explicitly noted as not accurately phase-aligning clocks, further emphasizes the motivation to devise a system that does achieve accurate phase alignment.

Claim 11: Field Programmable Gate Array System (External Phase Detector)

• Claimed Elements (Summary): An FPGA system similar to Claim 1, but with the phase detector located outside the FPGA. The FPGA provides output pins for the receiver-side and transmitter-side clock signals to the external phase detector. An internal phase controller receives the phase difference from the external detector and provides adjustment information to an external adjustable oscillator, which then generates the first wire rate clock signal for the serializer. The FPGA includes zero-delay buffer PLLs.
• Prior Art Baseline: The conventional FPGA (FIG. 1) provides the basic deserializer, serializer, and computational logic. The general knowledge of phase detectors, controllers, and adjustable oscillators is well established. The patent itself introduces the concept of an external phase detector and external adjustable oscillator in FIG. 4A. [Description, FIG. 4A: One difference between the system of FIG. 4A and the system of FIGS. 3A and 3B is that the phase detector 4206 is off-chip, i.e., not of the FPGA 4100.] It also teaches the use of zero-delay buffer PLLs (4208a, 4208b) to accurately transmit clock signals off-chip. [Description, FIG. 4A: The FPGA 4100 includes zero-delay buffer PLLS 4208a, 4208b.]
• Differences from Prior Art Baseline: The primary difference from Claim 1 is the placement of the phase detector and the adjustable oscillator outside the FPGA, with ZDBs facilitating accurate off-chip clock transmission.
• Motivation to Combine: A POSITA, motivated to achieve the same low-latency phase alignment as in Claim 1, might choose an external implementation for the phase detector and/or adjustable oscillator based on design considerations such as: if a higher-precision phase detector is only available off-chip, or if a centralized external clock source is preferred for managing multiple FPGAs or for specific noise/jitter performance requirements. The patent itself presents this configuration (FIG. 4A) as an alternative embodiment, indicating it is an obvious design choice for a POSITA. The use of zero-delay buffers (ZDBs) to transmit clock signals off-chip for accurate phase comparison without introducing significant deterministic delay is a known technique for managing clock integrity in system-level designs. The patent discusses "Any length mismatch between reference traces... may introduce a deterministic phase error" when dealing with external components, indicating these are known engineering challenges addressed by using appropriate components like ZDBs. [Description, FIG. 4A].

Claim 18: Method for Processing Data (Internal Phase Detector)

• Claimed Elements (Summary): A method for processing market data into order entry data using an FPGA system. The steps include receiving market data and a first clock, deserializing, generating a first receiver side clock, performing operations (a trading algorithm), generating an interim transmitter side clock, an internal phase detector comparing the receiver and interim transmitter clocks, an internal phase controller generating adjustment information, adjusting an internal adjustable oscillator to generate a wire rate clock, serializing, and transmitting order entry data.
• Prior Art Baseline: The method steps directly correspond to the operational flow of the system described in Claim 1. The patent explicitly states that "FPGAs are used in the financial industry in high frequency trading where the rapid processing of the FPGA is desired." [Definitions]. It also defines a "trading algorithm" as comprising parsing market data, performing mathematical operations, and generating order packets. [Definitions: the trading algorithm includes the steps of: (a) parsing market data; (b) performing mathematical operations at a portion of the market data; and (c) generating order packets using at least an output of (b).]
• Differences from Prior Art Baseline: The specific application of the phase-aligned FPGA system to processing "market data" into "order entry data" via a "trading algorithm."
• Motivation to Combine: Given the patent's explicit identification of HFT as an application for FPGAs where "rapid processing" is "desired," and the critical need to reduce latency in such applications, it would be an obvious application for a POSITA to employ the low-latency phase alignment system of Claim 1 (or its methodological equivalent) in an HFT context. The steps of a trading algorithm are well-known in the HFT domain. Therefore, applying the described latency-minimizing clock synchronization method to a known latency-critical application for FPGAs is an obvious combination.

Claim 29: Field Programmable Gate Array System (First Clock for Second Pin)

• Claimed Elements (Summary): An FPGA system similar to Claim 1, where the first reference clock pin receives a first clock signal, and the second reference clock pin also receives the same first clock signal. The system still includes the internal phase detector, controller, and adjustable PLL for phase alignment.
• Prior Art Baseline: The conventional FPGA (FIG. 1) shows an Oscillator or Clock Generator 122 providing a REFERENCE CLOCK signal, which is then fed to both the deserializer 104 and the transceiver PLL 108 (which ultimately influences the serializer 110). [Description, Conventional FPGA: a REFERENCE CLOCK signal is provided, by Oscillator or Clock Generator 122, to both the deserializer 104 and the serializer 110. The REFERENCE CLOCK signal is received by the serializer 110 via the transceiver PLL 108.]
• Differences from Prior Art Baseline: The explicit statement that the second reference clock pin receives the same first clock signal as the first reference clock pin, while retaining the internal phase alignment mechanism.
• Motivation to Combine: A POSITA would be motivated to simplify the clocking architecture of an FPGA system by utilizing a single, common external reference clock for both receive and transmit paths. This is a common design practice to ensure frequency coherence and simplify clock distribution. Even with a common reference clock, internal delays in the deserializer, computational logic, and serializer paths will inevitably lead to phase differences between the RXCLOCK and TXCLOCK. Therefore, it would be obvious for a POSITA to combine this simplified common reference clock input scheme (already present conceptually in FIG. 1) with the internal active phase alignment mechanism of Claim 1 to compensate for these internal phase discrepancies and maintain optimal low-latency operation.

Conclusion

The claims of US Patent 11018678 would likely be considered obvious under 35 U.S.C. § 103 given the explicit problem statement and the disclosed prior art within the patent itself. A POSITA, motivated to overcome the known latency drawbacks of conventional CDC circuits in FPGAs, would have reasonably combined known components such as phase detectors, control loops, and adjustable PLLs/oscillators into a feedback system for active phase alignment. The patent explicitly provides the problem, the conventional (problematic) solutions, and the fundamental building blocks for the claimed solution, and even describes various embodiments (internal vs. external components, common reference clocks) as alternative design choices. The application of this latency-reducing technology to high-frequency trading is also explicitly taught as a desirable use case for FPGAs.