Prior art

As a technical patent analyst, I need to access the official USPTO database to identify the most relevant prior art for US patent 10998017. Since direct access to live, queryable USPTO databases is not available to me, I will rely on the provided patent text, specifically the "Citations" section within the Google Patents record, which lists the prior art cited by the examiner. This approach prioritizes the search results, as per the operating rules.

Here's an analysis of the cited prior art from US10998017:

Most Relevant Prior Art for US Patent 10998017

The following prior art references were cited by the examiner and are listed in the patent document for US10998017. For each, I will provide the full citation, publication/filing date, a brief description (based on the title), and which claims it potentially anticipates under 35 U.S.C. § 102, focusing on the core elements of US10998017's claims: a DRAM with core, peripheral, and I/O units operating at specified low voltages for an eDP application.

1. US20050133852A1

• Full Citation: US20050133852A1, Jeng-Jye Shau, "High performance embedded semiconductor memory devices with multiple dimension first-level bit-lines"
• Publication Date: 2005-06-23 (Filing Date: 1996-05-24)
• Brief Description: This patent application describes high-performance embedded semiconductor memory devices with multi-dimensional bit-lines. While it deals with embedded memory, the title does not specifically mention DRAM, eDP, or low-voltage operation across different units as defined in US10998017.
• Potential Anticipation (35 U.S.C. § 102): Less likely to anticipate claims 1 or 2 directly based solely on the title, as it doesn't clearly disclose the specific low operating voltages for distinct units (core, peripheral, I/O) as claimed in US10998017 for an eDP application. However, if the detailed description reveals such voltage schemes for embedded DRAM, it could be relevant.

2. US20080117700A1

• Full Citation: US20080117700A1, Yutaka Nakamura, "Dynamic semiconductor storage device and method for operating same"
• Publication Date: 2008-05-22 (Filing Date: 2006-11-20)
• Brief Description: This patent application details a dynamic semiconductor storage device (which includes DRAM) and its operation method. The title suggests a focus on the device and its operational methodology, but doesn't explicitly mention embedded display ports or the specific low-voltage partitioning of US10998017.
• Potential Anticipation (35 U.S.C. § 102): Similar to the previous entry, without a deeper dive into the full text, it's difficult to ascertain direct anticipation of claims 1 or 2. It may describe aspects of DRAM operation but might not combine the specific voltage levels for core, peripheral, and I/O units, especially in the context of an eDP.

3. US20090067217A1

• Full Citation: US20090067217A1, [[Samsung Electronics Co.](/litigations/by-defendant/Samsung%20Electronics%20Co.), Ltd.](/litigations/by-plaintiff/Samsung%20Electronics%20Co.%2C%20Ltd.), "Methods for supplying power supply voltages in semiconductor memory devices and semiconductor memory devices using the same"
• Publication Date: 2009-03-12 (Filing Date: 2007-02-27)
• Brief Description: This reference focuses on methods and devices for supplying power supply voltages in semiconductor memory devices. This is highly relevant as US10998017's core invention revolves around specific low operating voltages for different DRAM units.
• Potential Anticipation (35 U.S.C. § 102): This reference could potentially anticipate aspects of claims 1 and 2, particularly if it discloses supplying different, specifically low voltages (below 1.1V) to the memory core, peripheral circuit, and/or input/output units of a DRAM. The explicit mention of "power supply voltages" makes this a strong candidate for disclosing voltage schemes that might overlap with US10998017, even if not explicitly for an eDP.

4. US20090122620A1

• Full Citation: US20090122620A1, Qualcomm Incorporated, "Systems and Methods for Low Power, High Yield Memory"
• Publication Date: 2009-05-14 (Filing Date: 2007-11-08)
• Brief Description: This patent application describes systems and methods for achieving low-power, high-yield memory. The "low power" aspect is directly aligned with the objective of US10998017.
• Potential Anticipation (35 U.S.C. § 102): This is another highly relevant reference. If this application discloses a DRAM with a memory core, peripheral circuit, and/or input/output unit operating at specific low voltages (especially below 1.1V) to achieve low power, it could potentially anticipate claims 1 and 2. While "embedded display port" might not be explicitly mentioned, the underlying technical solution of low-power DRAM could be similar.

5. US20100290300A1

• Full Citation: US20100290300A1, Nec Electronics Corporation, "Semiconductor integrated device"
• Publication Date: 2010-11-18 (Filing Date: 2009-05-14)
• Brief Description: This patent application describes a semiconductor integrated device. The broad title doesn't immediately suggest a direct overlap with the specific low-voltage DRAM architecture for eDP of US10998017.
• Potential Anticipation (35 U.S.C. § 102): Without further detail, it's difficult to determine direct anticipation of claims 1 or 2. It would require the detailed description to reveal a DRAM with the specific voltage partitioning and low voltage levels for core, peripheral, and I/O units as claimed in US10998017.

6. TWM276302U

• Full Citation: TWM276302U, Hsiuping Inst Technology, "DRAM of a 3-transistor cell"
• Publication Date: 2005-09-21 (Filing Date: 2005-04-08)
• Brief Description: This is a utility model patent describing a DRAM with a 3-transistor cell. While it describes a type of DRAM, it does not, from its title, indicate the specific power consumption or voltage partitioning of US10998017.
• Potential Anticipation (35 U.S.C. § 102): This reference focuses on the cell structure of DRAM. It is unlikely to anticipate claims 1 or 2, which are directed to the power supply architecture of a DRAM for an eDP, including specific low voltages for different functional units, rather than the internal cell design itself.

7. TWI355590B

• Full Citation: TWI355590B, Giga Byte Tech Co Ltd, "Common module for ddrii sdram and ddriii sdram"
• Publication Date: 2012-01-01 (Filing Date: 2007-05-15)
• Brief Description: This patent describes a common module for DDRII SDRAM and DDRIII SDRAM, indicating compatibility across different DDR generations. This is relevant to the "DDR I, low power DDR I, DDR II, and low power DDR II specification" compatibility mentioned in US10998017.
• Potential Anticipation (35 U.S.C. § 102): This reference might be relevant for its discussion of DDR specifications and compatibility, which US10998017 also mentions. However, it's less likely to directly anticipate the specific low operating voltages (below 1.1V) for the memory core, peripheral circuit, and input/output units as claimed in US10998017, unless its detailed description delves into such a low-voltage power architecture.

Based on the titles and general descriptions, US20090067217A1 ("Methods for supplying power supply voltages in semiconductor memory devices and semiconductor memory devices using the same") and US20090122620A1 ("Systems and Methods for Low Power, High Yield Memory") appear to be the most relevant prior art references. Their focus on power supply voltages and low-power memory directly addresses key inventive aspects of US10998017, which claims a DRAM operating its core, peripheral, and I/O units at low voltages (specifically below 1.1V for peripheral and I/O) for eDP applications. To confirm actual anticipation under 35 U.S.C. § 102, a detailed claim-by-claim analysis against the full text of these references would be necessary to determine if every element of claims 1 and 2 of US10998017 is present in any single prior art reference.