Obviousness

Obviousness Analysis under 35 U.S.C. § 103

This analysis addresses the obviousness of US patent 10998017 under 35 U.S.C. § 103, considering the scope and content of the prior art, the differences between the prior art and the claimed invention, and the level of ordinary skill in the art at the time of the invention (priority date: July 17, 2012). A Person Having Ordinary Skill in the Art (PHOSITA) in this field would be an electrical engineer or a computer architect with experience in semiconductor memory design, particularly dynamic random access memory (DRAM) and display interfaces, familiar with power management techniques.

Background and Motivation for a PHOSITA

The patent itself identifies a key problem in the prior art: while the Panel Self Refresh (PSR) function in embedded DisplayPort (eDP) version 1.3 significantly reduces Graphics Processing Unit (GPU) power consumption, the power consumption of the timing controller—due to its DRAM frame buffer—increases. The patent explicitly states, "Therefore, how to design the frame buffer to reduce the power consumption of the timing controller becomes an important issue of memory manufacturers." [cite: "the panel self refresh function can make power consumption of the graphic processing unit be significantly reduced, power consumption of the timing controller is increased due to operation of the frame buffer. Therefore, how to design the frame buffer to reduce the power consumption of the timing controller becomes an important issue of memory manufacturers." from Definitions section] It further notes that JEDEC-specified operation voltages for various DDR generations, even low-power ones (e.g., LPDDR II peripheral/I/O at 1.14V-1.30V), "can not satisfy requirements (that is, the low operation power consumption and the low standby power consumption) of the embedded display port (eDP) version 1.3." [cite: "But, the operation voltages specified by the Joint Electron Device Engineering Council (as shown in Table I) can not satisfy requirements (that is, the low operation power consumption and the low standby power consumption) of the embedded display port (eDP) version 1.3." from Description section]

This establishes a clear motivation for a PHOSITA to seek further reductions in DRAM power consumption for eDP applications, even beyond existing low-power JEDEC standards, particularly by exploring lower operating voltages.

Analysis of Independent Claim 1

Independent claim 1 of US10998017 describes a DRAM comprising:

1. A DRAM core cell operating at a first voltage lower than 1.1V.
2. A peripheral circuit electrically connected to the DRAM core cell, operating at a second voltage lower than 1.1V.
3. The DRAM core cell and peripheral circuit are formed on a single chip, with the peripheral circuit external to the core cell.
4. The first and second voltages enable the DRAM to be applied to an eDP.

A PHOSITA, motivated by the stated need for lower power consumption in eDP applications, would find the claimed invention obvious when combining the teachings of several prior art references.

Proposed Combination 1: US20090067217A1 (Samsung) + US20090122620A1 (Qualcomm) + US20050133852A1 (Shau) + General Knowledge of eDP 1.3.

• US20050133852A1 (Shau): This patent, titled "High performance embedded semiconductor memory devices," teaches the integration of semiconductor memory devices with multiple components on a single chip. [cite: US20050133852A1] A PHOSITA would readily understand from Shau the concept of forming a DRAM core cell and its peripheral circuits on a single chip, as recited in claim 1. [cite: US20050133852A1]

• US20090067217A1 (Samsung): This reference, "Methods for supplying power supply voltages in semiconductor memory devices and semiconductor memory devices using the same," explicitly teaches varying power supply voltages to different blocks of memory (e.g., internal voltage, external voltage) to achieve low power consumption. [cite: US20090067217A1] It discloses supplying independent power supply voltages to a core voltage generating block, a peripheral circuit voltage generating block, and an I/O circuit voltage generating block. [cite: US20090067217A1] This reference provides the motivation and technical approach for supplying separate, optimized voltages to the DRAM core and peripheral circuits.

• US20090122620A1 (Qualcomm): Titled "Systems and Methods for Low Power, High Yield Memory," this patent reinforces the concept of operating memory devices at reduced voltages to minimize power consumption and enhance yield. [cite: US20090122620A1] It specifically discusses adaptively scaling voltages to achieve desired performance and power targets. [cite: US20090122620A1] This would further motivate a PHOSITA to target low operating voltages for all components of the DRAM.

• General Knowledge of eDP 1.3: The patent itself establishes that eDP 1.3 with its PSR function creates a demand for DRAM frame buffers with significantly lower power consumption than what existing JEDEC standards offer. [cite: "the embedded display port version 1.3 published by the Video Electronics Standards Association adds a panel self refresh (PSR) function, where the panel self refresh function can make a graphic processing unit (GPU) turn off connection between the graphic processing unit and a liquid crystal panel when a frame displayed on the liquid crystal panel is frozen." from Definitions section] [cite: "But, the operation voltages specified by the Joint Electron Device Engineering Council (as shown in Table I) can not satisfy requirements (that is, the low operation power consumption and the low standby power consumption) of the embedded display port (eDP) version 1.3." from Description section]

Motivation to Combine:
A PHOSITA, recognizing the critical need to reduce power consumption of the DRAM frame buffer in an eDP 1.3 system (as articulated in the '017 patent's background), would look to known power-saving techniques in DRAM design. They would be motivated to combine the single-chip integration of embedded memory (Shau '852) with the independent voltage control and adaptive voltage scaling for low power (Samsung '217 and Qualcomm '620). Knowing that even existing low-power JEDEC standards (like LPDDR II at 1.14V-1.30V for peripheral/I/O) were deemed insufficient, a PHOSITA would be driven to push these voltages even lower. The selection of "< 1.1V" for the peripheral circuit and core cell, while requiring careful engineering to maintain reliability and performance, would be a logical step in response to the strong motivation to meet the specific, stringent power requirements of the eDP 1.3 application. The phrase "capable of making the DRAM be applied to an embedded display port (eDP)" merely describes the intended function of the low-voltage DRAM, and this application is clearly motivated by the known problems in the prior art.

Analysis of Dependent Claim 2

Dependent claim 2 adds an input/output (I/O) unit to the DRAM of claim 1, which is electrically connected to the peripheral circuit and the DRAM core cell, and operates in a third voltage lower than 1.1V.

Proposed Combination for Claim 2: The combination for Claim 1 (US20090067217A1 (Samsung) + US20090122620A1 (Qualcomm) + US20050133852A1 (Shau) + General Knowledge of eDP 1.3) would render claim 2 obvious.

Motivation to Combine:
Samsung '217 explicitly teaches supplying independent power supply voltages to various blocks, including an "I/O circuit voltage generating block." [cite: US20090067217A1] Given the overarching goal of minimizing total DRAM power consumption for eDP 1.3 applications, a PHOSITA would naturally extend the voltage reduction strategy to the I/O unit as well. Since JEDEC LPDDR II already operated I/O at 1.14V-1.30V, and this was insufficient for eDP 1.3's demanding power profile, further lowering the I/O voltage to below 1.1V would be a straightforward application of the same power-saving principles motivated by the context of eDP. Reducing the voltage on all active components, including the I/O unit, would be an obvious design choice for a PHOSITA aiming to achieve the stated power consumption goals.