Obviousness

Obviousness Analysis of US Patent 10,734,4481 Under 35 U.S.C. § 103

This analysis assesses whether the claims of US Patent 10,734,4481, which describe semiconductor devices with graded dopant regions, would have been obvious to a person having ordinary skill in the art (PHOSITA) at the time of the invention (priority date September 3, 2004) based on the cited prior art. The key distinguishing feature of the independent claims (Claim 1 and Claim 20) is the use of a graded dopant concentration within active regions and/or adjacent well regions to aid carrier movement from the first surface to the second surface of the substrate, typically to sweep unwanted minority carriers deep into the substrate.

Independent Claims Overview

• Claim 1 describes a semiconductor device with a substrate, first and second active regions (where transistors are formed) on the first surface, and the critical elements being "at least a portion of at least one of the first and second active regions having at least one graded dopant concentration to aid carrier movement from the first surface to the second surface of the substrate" and "at least one well region adjacent to the first or second active region containing at least one graded dopant region, the graded dopant region to aid carrier movement from the first surface to the second surface of the substrate."
• Claim 20 is substantially similar to Claim 1, reinforcing the use of graded dopants in active and/or well regions to aid carrier movement from the surface to the substrate.

The patent itself acknowledges that "Retrograde wells have been attempted, with little success, to help improve soft error immunity in SRAMs and visual quality in imaging circuits" and that "Efforts have been made in graded base transistors to create an aiding drift field to enhance the diffusing minority carrier's speed from emitter to collector." This indicates that the general concepts of graded doping and retrograde wells, and their application to carrier management, were known in the prior art. The novelty lies in the specific application to active regions and adjacent well regions to sweep carriers from the surface to the substrate for a broader range of performance improvements.

Prior Art Combinations and Motivation for Combination

Several prior art references, individually or in combination, teach elements of the claimed invention and suggest a motivation for a PHOSITA to combine them to achieve the claimed outcome.

Combination 1: US4481522A (RCA Corporation) and US6310366B1 (Micron Technology, Inc.)

• US4481522A (CCD Imagers with substrates having drift field): This patent, published in 1984, describes Charge Coupled Device (CCD) imagers where a drift field is created in the substrate to aid carrier movement. Specifically, it discloses a CCD imager having a substrate of a first conductivity type, and an active region on the surface with a doping profile that creates an electric field to "collect photogenerated carriers and to sweep them rapidly into the CCD channels". While focused on CCDs and collection into channels, it clearly teaches the concept of creating a drift field via doping in a semiconductor body to manipulate carrier movement.
• US6310366B1 (Retrograde well structure for a CMOS imager): This patent, published in 2001, explicitly describes a CMOS imager with a "retrograde well structure for reducing dark current in an image sensor." A retrograde well inherently has a graded dopant concentration, typically increasing in concentration with depth, to establish an electric field. The purpose here is to sweep minority carriers away from the active light-sensing regions (the surface) to reduce dark current. The abstract states it "reduces dark current by causing minority carriers to recombine away from the light detecting regions."

Obviousness Argument:
A PHOSITA, familiar with the concept of using drift fields generated by doping gradients to manage charge carriers in semiconductor devices (as taught by US4481522A), would have been motivated to apply similar principles to CMOS imagers, especially to address known problems like dark current and soft errors. US6310366B1 directly provides this motivation and solution by teaching a retrograde well structure in a CMOS imager to sweep minority carriers away from the surface (active regions) for improved performance (reduced dark current).

The combination of these references demonstrates that:

1. Graded doping (implicitly present in retrograde wells) was known.
2. The purpose of such doping was to create drift fields to aid carrier movement.
3. This technique was applied in the context of imagers (CMOS imagers specifically by US6310366B1).
4. The desired outcome was to sweep carriers away from the active surface regions towards the bulk/substrate to improve performance.

The claims of US10734481, calling for graded dopant concentrations in active regions or adjacent well regions to aid carrier movement from the first surface to the second surface of the substrate, would have been an obvious design choice for a PHOSITA seeking to optimize carrier collection and reduce noise in CMOS imagers, given the teachings of these prior arts. The general goal of improving "visual quality including pixel resolution and color sensitivity for imaging ICs" is directly addressed by reducing dark current.

Combination 2: US20030042511A1 (Rhodes Howard E.) and US20070045682A1 (Hong Sungkwon C)

• US20030042511A1 (CMOS imager and method of formation): This publication from 2003 describes a CMOS imager and explicitly discusses the need to "collect generated carriers in a timely and efficient manner" and mentions the use of "an optional n-type epitaxial layer with a varying doping concentration" for charge collection. It also discusses wells for forming n-channel and p-channel devices. This teaches a CMOS imager with wells and varying doping concentrations to manage carriers.
• US20070045682A1 (Imager with gradient doped EPI layer): Although published after the priority date of US10734481, this is listed as prior art, indicating it relates to an earlier application or similar technology. It describes an imager device comprising a "gradient doped EPI layer". It explicitly notes that "the graded doping of the epitaxial layer creates an electric field which sweeps carriers to an intended region." While the context of its own filing might be later, the content points to the knowledge base prior to the invention of US10734481.
• US6753202B2 (CMOS photodiode having reduced dark current and improved light sensitivity and responsivity): This 2004 patent, which shares the same priority date (September 3, 2004) as US10734481, nevertheless demonstrates the contemporary state of the art. It describes a CMOS photodiode with a "drift region" formed by a "buried p+ layer within the epitaxial layer" to "draw photogenerated electrons toward the photodiode" and reduce dark current. This structure effectively creates a graded dopant profile to aid carrier movement.

Obviousness Argument:
A PHOSITA, aiming to improve carrier management and reduce noise in CMOS imagers (as discussed in US20030042511A1), would have recognized the benefit of a gradient doped layer to sweep carriers. US20070045682A1 explicitly provides the concept of a "gradient doped EPI layer" to create an electric field that sweeps carriers to an "intended region". US6753202B2 further exemplifies the use of doping profiles (e.g., buried p+ layer) to create drift fields for efficient carrier collection and dark current reduction in CMOS photodiodes, which are active regions within imagers.

The motivation to combine these would be to integrate the known benefits of graded doping (creating drift fields for carrier movement) into the active and well regions of CMOS imagers to improve their performance, specifically by sweeping unwanted minority carriers away from the surface. This directly aligns with the stated goals of US10734481 for "better visual quality including pixel resolution and color sensitivity for imaging ICs." The "subterranean n− layer has a graded donor concentration to sweep the minority carriers deep into the substrate" described in US10734481 is functionally and structurally analogous to the "gradient doped EPI layer" or the drift field created by doping variations as discussed in these prior art examples.

General Motivation for Combining Graded Dopants in Active/Well Regions

Beyond specific combinations, the background section of US10734481 itself reveals the PHOSITA's understanding:

• The concept of "aiding drift electric field" created by "donor gradient" in graded base BJTs to help carrier transverse from emitter to collector was known, leading to improved frequency of operation.
• The problems of "spurious minority carriers" in digital VLSI logic, DRAMs (degradation of refresh time), and digital imaging ICs (degradation of CMOS digital images, pixel and color resolution) were well-recognized.
• Existing techniques like "retrograde and halo wells" were already attempted to improve refresh time in DRAMs and reduce dark current in digital camera ICs, with the goal of "divert[ing] the minority carriers away from the active regions of critical charge storage nodes at the surface".

Given this context, a PHOSITA would have been highly motivated to:

1. Apply the known principle of graded dopants creating aiding drift fields (from BJT technology) to other semiconductor devices, particularly MOS devices and integrated circuits where carrier management is critical.
2. Improve upon existing retrograde/halo well techniques by optimizing the "graded dopant concentration" within active regions and adjacent wells to more effectively "sweep the minority carriers deep into the substrate", thereby addressing issues like soft errors, refresh time degradation, and dark current.
3. Recognize that optimizing carrier movement through graded dopants in these specific regions (active and well regions) would lead to performance enhancements across various applications, including digital logic, DRAM, nonvolatile memory, and image sensors, as explicitly identified in the patent's abstract.

The "new challenges" for IGBTs mentioned in the background also point to the need for "different dopant gradients either in the same layer at different positions, or at the interfaces of similar or dissimilar layers" for optimal electron transit and hole recombination. This reinforces the motivation for exploring graded dopants in various device regions to achieve specific performance goals.

Conclusion

Based on the analysis of the prior art cited within US10734481, particularly US4481522A, US6310366B1, US20030042511A1, and US6753202B2, and considering the general knowledge acknowledged in the patent's background, the claims of US10734481 would likely be found obvious. A person having ordinary skill in the art, facing known challenges with unwanted minority carriers in various semiconductor devices, would have been motivated to combine the established principles of drift fields generated by graded dopants with existing device structures (e.g., active regions, wells) to sweep these carriers away from active surface areas and into the substrate, thereby improving device performance as described in the patent. The innovation appears to be an application of known principles to achieve predictable results in new contexts, rather than a non-obvious leap.