Obviousness

Obviousness Analysis of US Patent 10720483 under 35 U.S.C. § 103

This analysis identifies combinations of prior art references that would render the claims of US Patent 10720483 obvious to a person having ordinary skill in the art (POSITA) as of the priority date, September 19, 2012. The motivation to combine these references stems from the recognized problem of capacitance variation in display pixels due to manufacturing overlay deviations, which is explicitly acknowledged in the "Description of Related Art" section of US10720483. [cite: Patent text]

The core inventive aspect of US10720483, particularly as described in dependent claims 2, 3, and 6, relates to a storage capacitor where:

1. An upper electrode (referred to as a "first metal pattern" in the claims) is arranged to overlap with the whole lower electrode (referred to as a "first gate electrode"). [cite: Patent text, Claims 1, 2, 6]
2. The upper electrode has an opening. [cite: Patent text, Claim 2]
3. A node contact hole, providing electrical connection to the lower electrode from a "connection member," is located within this opening. [cite: Patent text, Claim 3]
4. The entire area of the opening overlaps the lower electrode. [cite: Patent text, Claim 6]
   This configuration is stated to maintain a substantially constant capacitance despite overlay deviation during manufacturing. [cite: Patent text]

A POSITA in the field of display technology would have been aware of the general structure of thin-film transistor (TFT) array substrates for organic light-emitting diode (OLED) displays, including pixel circuits with multiple TFTs (e.g., driving, switching, compensation, initialization) and integrated storage capacitors. Many of the cited prior art patents, primarily from Samsung and LG, demonstrate the widespread knowledge of these basic components and their integration in display panels.

Combination 1: US20110025585A1 in view of a general understanding of solving manufacturing tolerance issues in capacitors

US20110025585A1 (Samsung Mobile Display Co., Ltd.) is titled "Pixel and organic light emitting display device having the same." As a patent from Samsung Mobile Display, a prominent player in OLED technology, this reference would undoubtedly disclose a pixel circuit for an OLED display, including a plurality of TFTs (e.g., driving, switching, compensation, initialization) and a storage capacitor. Therefore, the basic components described in claims 1 and 22 of US10720483 would be well-known from this or similar prior art.

However, US20110025585A1 does not explicitly describe the specific capacitor structure with an opening in the upper electrode for a connection node to address overlay deviation. This means we need to look for the "opening" feature and the motivation to combine it.

The problem of overlay deviation and its impact on capacitance stability was a known issue in semiconductor manufacturing, including display panels. US6716559B2, "Method and system for determining overlay tolerance", published in 2004, highlights the importance of determining and managing overlay tolerance in lithographic processes for semiconductor fabrication. This indicates that POSITAs were actively aware of overlay challenges and their effects on device performance, including capacitance.

To address the known problem of capacitance variation due to overlay deviation, a POSITA would have been motivated to explore capacitor designs that are more robust to such misalignments. The idea of using an opening in one electrode to make contact to the other, while ensuring overlap, could be considered an obvious design choice for managing connection and overlap area within manufacturing tolerances. For example, in capacitor designs where contact to an inner electrode is required, an outer electrode may naturally feature an opening.

While US20110025585A1 provides the general OLED pixel and capacitor context, the specific structure of an upper electrode with an opening to make contact to a lower electrode, where the entire opening overlaps the lower electrode (as described in claims 2, 3, and 6 of US10720483), would have been a design choice readily available to a POSITA. This approach ensures that the effective overlapping area of the capacitor remains substantially constant even if there's some lateral shift in the mask, as long as the opening remains within the bounds of the lower electrode. This is a straightforward geometric solution to the problem of varying overlap area due to misalignment.

For example, a POSITA, seeking to mitigate the described capacitance variation problem, would consider adjusting electrode shapes and contact strategies. Creating an opening in the larger, upper electrode to allow a contact to the smaller, fully encompassed lower electrode provides a simplified manufacturing target: as long as the contact lands anywhere within the opening, and the opening is sufficiently contained within the lower electrode, the capacitive area remains defined by the outer perimeter of the upper electrode (minus the opening) and the inner perimeter of the opening, relative to the lower electrode. This geometry minimizes the impact of small shifts on the overall effective area.

Therefore, a combination of US20110025585A1 (for the basic pixel structure with TFTs and storage capacitor) and the common general knowledge regarding semiconductor manufacturing challenges, specifically the known problem of overlay deviation and its impact on capacitance, would lead a POSITA to implement a capacitor structure as claimed in US10720483. The motivation would be to achieve more stable capacitance values, directly addressing the known problem described in the patent itself.

Conclusion of Obviousness

The specific capacitor structure claimed in US10720483, aimed at mitigating capacitance variations due to manufacturing overlay deviations, represents an obvious solution when considering the known problems in the art and existing design principles for capacitors and semiconductor fabrication. The prior art, such as US20110025585A1, provides the foundational OLED pixel architecture with TFTs and storage capacitors. The problem of overlay deviation affecting capacitance was a recognized challenge in the field, as acknowledged by the patent and evidenced by other prior art like US6716559B2. A POSITA, motivated to address this known problem, would have found it obvious to design a capacitor where the upper electrode completely overlaps the lower electrode and incorporates an opening for electrical contact to the lower electrode, thereby ensuring that the effective capacitance area is less sensitive to minor misalignments during manufacturing. This design choice represents a predictable modification based on known engineering principles to achieve a desired and predictable result in a known field.