Patent 10720483
Derivative works
Defensive disclosure: derivative variations of each claim designed to render future incremental improvements obvious or non-novel.
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Derivative works
Defensive disclosure: derivative variations of each claim designed to render future incremental improvements obvious or non-novel.
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Defensive Disclosure: Derivative Works for US Patent 10720483
This document outlines a series of derivative works based on US Patent 10720483, "Thin film transistor array substrate and organic light-emitting diode display." The objective is to establish prior art that would render future incremental improvements by competitors as obvious or non-novel, focusing on the core inventive concepts of the patent, particularly the stable capacitor structure and its connection within a TFT array. The analysis leverages the patent's independent claims 1 and 22 as foundational elements.
Derivatives for Claim 1: General TFT Array Substrate with Capacitor and Connection
Claim 1: A thin film transistor (TFT) array substrate comprising: a substrate; a first thin film transistor including a first channel region and a first gate electrode overlapping the first channel region, the first gate electrode and the first channel region being spaced apart from each other with a first insulating layer therebetween; a second thin film transistor including a second channel region and a second gate electrode overlapping the second channel region, the second gate electrode and the second channel region being spaced apart from each other with the first insulating layer therebetween; a second insulating layer disposed on the first and second gate electrode; a first metal pattern overlapping the first gate electrode, the first metal pattern and the first gate electrode being spaced apart from each other with the second insulating layer therebetween; a third insulating layer disposed on the first metal pattern; and a connection member disposed on the third insulating layer and electrically connecting the first gate electrode and the second thin film transistor.
1. Material & Component Substitution
Derivative 1.1: High-k Dielectric Storage Capacitor
- Enabling Description: The second insulating layer, serving as the dielectric for the storage capacitor formed by the first gate electrode (lower plate) and the first metal pattern (upper plate), is replaced with a high-k dielectric material, specifically Hafnium Dioxide (HfO2). This material exhibits a dielectric constant significantly higher than silicon nitride (SiNx) or silicon oxide (SiO2), enabling a substantial increase in capacitance density per unit area. HfO2 deposition is performed using Atomic Layer Deposition (ALD) at temperatures between 250°C and 400°C, ensuring conformal coverage and excellent film uniformity over the patterned first gate electrode. The first and third insulating layers can remain conventional SiNx or SiO2, providing inter-layer isolation. The connection member, typically a metallic alloy, maintains its electrical coupling to the first gate electrode through contact holes, which are dry-etched through the HfO2 and overlying insulating layers.
graph TD A[Substrate] --> B{First Insulating Layer (SiNx)}; B --> C1[First Channel Region]; B --> C2[Second Channel Region]; B --> D1[First Gate Electrode]; B --> D2[Second Gate Electrode]; D1 -- overlaps --> C1; D2 -- overlaps --> C2; D1 & D2 --> E{Second Insulating Layer (High-k Dielectric: HfO2)}; E --> F[First Metal Pattern]; F -- overlaps --> D1; F --> G{Third Insulating Layer (SiNx)}; G --> H[Connection Member]; H -- electrically connects --> D1; H -- electrically connects --> C2 (Second TFT drain/source); subgraph High-k Capacitor D1 -- Dielectric (HfO2) --> F; end
Derivative 1.2: Flexible Polyimide Substrate with IGZO TFTs
- Enabling Description: The rigid substrate is replaced with a flexible polyimide (PI) film, such as Kapton E, for applications requiring mechanical flexibility. All active semiconductor layers for the first and second TFTs are fabricated using amorphous Indium Gallium Zinc Oxide (IGZO) as the channel material, deposited by sputtering at temperatures compatible with PI (~200°C). IGZO TFTs offer superior uniformity and lower processing temperatures compared to polysilicon, making them ideal for flexible electronics. The first, second, and third insulating layers are deposited using low-temperature plasma-enhanced chemical vapor deposition (PECVD) of SiNx or SiO2. All electrode materials (gate, source, drain, first metal pattern, and connection member) are selected from flexible, high-conductivity metallic alloys, such as a Mo/Al/Mo stack (molybdenum/aluminum/molybdenum), patterned via standard photolithography and dry etching processes adapted for polymer substrates.
graph TD A[Flexible Polyimide Substrate] --> B{First Insulating Layer (PECVD SiNx)}; B --> C1[IGZO First Channel Region]; B --> C2[IGZO Second Channel Region]; B --> D1[First Gate Electrode (Mo/Al/Mo)]; B --> D2[Second Gate Electrode (Mo/Al/Mo)]; D1 -- overlaps --> C1; D2 -- overlaps --> C2; D1 & D2 --> E{Second Insulating Layer (PECVD SiOx)}; E --> F[First Metal Pattern (Mo/Al/Mo)]; F -- overlaps --> D1; F --> G{Third Insulating Layer (PECVD SiNx)}; G --> H[Connection Member (Mo/Al/Mo)]; H -- electrically connects --> D1; H -- electrically connects --> C2 (Second TFT drain/source); subgraph Flexible IGZO TFT Array C1; C2; D1; D2; F; H; end
2. Operational Parameter Expansion
Derivative 1.3: Ultra-low Power TFT Array with Depletion-Mode Capacitors for Energy Harvesting
- Enabling Description: The TFT array substrate is optimized for ultra-low power operation in energy-harvesting applications, where display updates are infrequent but data retention is critical. The first and second TFTs are designed as depletion-mode transistors, utilizing a specific channel doping profile (e.g., n-type implantation for normally-on operation) and a gate electrode work function tuned to minimize quiescent current. The storage capacitor (formed by the first gate electrode and first metal pattern) is characterized by an ultra-thin second insulating layer (e.g., ~10-20 nm SiOx) with optimized stoichiometry to achieve extremely low leakage current (femtoampere range), ensuring long-duration charge retention (several minutes to hours) even with minimal refresh. The connection member employs highly conductive interconnects and contact materials (e.g., copper with barrier layers) to minimize resistive losses during signal routing, allowing for efficient integration with low-voltage energy harvesting circuits and sparse display updates.
graph TD A[Substrate] --> B{First Insulating Layer}; B --> C1[Depletion-Mode First Channel Region]; B --> C2[Depletion-Mode Second Channel Region]; B --> D1[First Gate Electrode]; D1 -- overlaps --> C1; D2 -- overlaps --> C2; D1 & D2 --> E{Second Insulating Layer (Ultra-thin, Low-Leakage Dielectric)}; E --> F[First Metal Pattern]; F -- overlaps --> D1; F --> G{Third Insulating Layer}; G --> H[Connection Member (High-Conductivity)]; H -- electrically connects --> D1; H -- electrically connects --> C2 (Second TFT drain/source); subgraph Energy Harvesting Optimization C1 & C2 -- Depletion-Mode --> I[Minimised Quiescent Current]; E -- Ultra-thin --> J[Long Charge Retention]; H -- High-Conductivity --> K[Efficient Signal Routing]; end
Derivative 1.4: High-Temperature (200°C+) Operation with SiC TFTs for Industrial Monitoring
- Enabling Description: The TFT array substrate is engineered for continuous operation at temperatures exceeding 200°C, typical of industrial process monitoring or downhole applications. The substrate consists of a thermally stable ceramic material, such as high-purity alumina (Al2O3). The semiconductor layers for the first and second TFTs are fabricated from polycrystalline Silicon Carbide (SiC) thin films, deposited via chemical vapor deposition (CVD) due to its wide bandgap and high electron mobility at elevated temperatures. All insulating layers (first, second, third) are composed of high-density, low-stress Al2O3 or SiOx, deposited through high-temperature sputtering or CVD processes. Electrode materials, including the gate electrodes, first metal pattern, and connection member, are selected from refractory metals like Tungsten (W) or Molybdenum (Mo), which maintain structural integrity and electrical conductivity without electromigration or oxidation at the specified operational temperatures. The capacitor's dielectric properties must remain stable across the entire temperature range.
graph TD A[Alumina Substrate (High-Temp)] --> B{First Insulating Layer (High-density SiOx)}; B --> C1[SiC First Channel Region]; B --> C2[SiC Second Channel Region]; B --> D1[First Gate Electrode (Refractory Metal - W)]; B --> D2[Second Gate Electrode (Refractory Metal - W)]; D1 -- overlaps --> C1; D2 -- overlaps --> C2; D1 & D2 --> E{Second Insulating Layer (Al2O3)}; E --> F[First Metal Pattern (Refractory Metal - Mo)]; F -- overlaps --> D1; F --> G{Third Insulating Layer (High-density SiOx)}; G --> H[Connection Member (Refractory Metal - Mo)]; H -- electrically connects --> D1; H -- electrically connects --> C2 (Second TFT drain/source); subgraph High-Temperature Robust Array C1 & C2 -- SiC TFTs --> I[Thermal Stability >200C]; D1 & D2 & F & H -- Refractory Metals --> J[Reliable Electricals]; end
3. Cross-Domain Application
Derivative 1.5: Integrated Chemical Sensor Array for Precision Agriculture
- Enabling Description: The TFT array substrate is repurposed as a distributed chemical sensor array for precision agriculture. The first TFT acts as a sensitive readout transistor, while the storage capacitor is integral to a chemically-sensitive field-effect structure (ChemFET). The first gate electrode (lower capacitor plate) is exposed via selective etching of the overlying insulating layers and coated with a functionalized sensing material, such as a specific ion-selective polymer membrane (e.g., PVC-based membrane with valinomycin for potassium ion detection) or an enzyme-immobilized layer for glucose sensing in plant sap. The "second TFT" on the same substrate serves as a reference transistor or part of a differential measurement circuit to compensate for environmental drift. The connection member routes the gate voltage from the sensing element to the first TFT's channel, enabling a voltage change induced by chemical interaction to be transduced into a measurable current. This array provides real-time, in-situ nutrient levels in soil or plant tissue.
graph TD A[Substrate] --> B{First Insulating Layer}; B --> C1[First Channel Region (Sensor Readout TFT)]; B --> D1[First Gate Electrode (Lower Capacitor/Sensing Plate)]; D1 -- exposed & coated --> E[Chemically Selective Layer (e.g., K+ membrane)]; E -- interacts with --> F[Analyte (e.g., Soil K+)]; C1 -- overlaps --> D1; D1 --> G{Second Insulating Layer}; G --> H[First Metal Pattern (Upper Capacitor Plate)]; H -- overlaps --> D1; H --> I{Third Insulating Layer}; I --> J[Connection Member]; J -- electrically connects --> D1; J --> K[Second TFT (Reference/Amplifier)]; subgraph Precision Ag Sensor System F --> E; E --> D1; D1 --> J; J --> L[Readout Circuitry]; L -- to --> M[Wireless Transmitter (e.g., LoRa)]; end
Derivative 1.6: Dynamic Haptic Feedback Array for Advanced Prosthetics
- Enabling Description: The TFT array substrate is configured as a flexible, high-resolution haptic feedback matrix for prosthetic limbs. Each "pixel" in the array is integrated with a micro-actuator for localized pressure or vibration feedback. The first TFT controls the driving voltage for a piezoelectric element or electrostatic actuator. The storage capacitor (first gate electrode and first metal pattern, separated by the second insulating layer) serves as a charge reservoir for the haptic actuator, providing the necessary transient current for quick response times. The first gate electrode is directly connected to one terminal of the piezoelectric element, and the first metal pattern forms the other. The second insulating layer acts as the piezoelectric material itself (e.g., AlN) or a high-capacitance dielectric for the electrostatic actuator. The second TFT acts as a local switch or feedback element for the haptic intensity. The connection member routes digital control signals from an embedded microcontroller to activate specific haptic points, creating programmable tactile sensations on the prosthetic skin.
graph TD A[Flexible Polyimide Substrate] --> B{First Insulating Layer}; B --> C1[First Channel Region (TFT Control)]; B --> D1[First Gate Electrode (Actuator Terminal 1)]; D1 -- overlaps --> C1; D1 --> E{Second Insulating Layer (Piezoelectric Material/Dielectric)}; E --> F[First Metal Pattern (Actuator Terminal 2)]; F -- overlaps --> D1; F --> G{Third Insulating Layer}; G --> H[Connection Member]; H -- electrically connects --> D1; H --> I[Second TFT (Switch/Feedback)]; subgraph Haptic Array for Prosthetics C1 -- controls voltage --> E & F; E & F -- generate --> J[Localized Haptic Feedback]; H --> K[Microcontroller/Control Logic]; K --> L[Prosthetic User Interface]; end
4. Integration with Emerging Tech
Derivative 1.7: AI-Driven Self-Correcting Display Panel with Predictive Maintenance
- Enabling Description: The TFT array substrate is augmented with embedded micro-sensors (e.g., temperature, voltage, luminance feedback from test pixels) and an on-chip AI accelerator. During manufacturing and throughout the display's operational life, performance parameters (e.g., threshold voltage (Vth) drift of the first TFT, actual capacitance of the storage capacitor (first gate electrode and first metal pattern), pixel luminance) are continuously monitored. This data is fed to the integrated AI neural network, which utilizes a pre-trained model to predict potential failures, compensate for aging effects, and dynamically adjust pixel driving signals. The connection member routes these AI-generated compensation signals to the gate and data lines of the first TFTs, allowing for real-time, adaptive correction of display uniformity and color balance. The second TFTs can act as multiplexers for sensor readout. This system actively prevents display degradation and informs predictive maintenance schedules.
graph TD A[TFT Array Substrate] --> B[First TFT (Driving TFT)]; A --> C[Storage Capacitor]; B -- output --> D[OLED (not shown)]; C -- maintains Vgs --> B; A --> E[Embedded Sensors (Temp, V, Luminance)]; E -- measures --> F[Performance Data (Vth, Cst, Luminance)]; F --> G[On-Chip AI Accelerator (Neural Network)]; G -- analyzes & predicts --> H[Compensation Values & Predictive Maintenance Alarms]; H --> I[Integrated Microcontroller Unit]; I -- adjusts --> B[First TFT Driving Parameters]; I -- adjusts --> J[Display Driver IC (not shown)]; subgraph AI Self-Correction & Prediction G -- trained with --> K[Historical Performance/Failure Data]; I -- real-time adjustment --> B; H --> L[Maintenance System]; end
Derivative 1.8: IoT-Enabled Environmental Sensor Matrix with Edge Computing
- Enabling Description: The TFT array substrate is transformed into an IoT-enabled environmental sensor matrix, equipped with edge computing capabilities for smart building or industrial environments. Each "pixel" integrates a micro-sensor (e.g., an NDIR gas sensor for CO2, a resistive humidity sensor) with the first TFT, which acts as a transducer or amplifier. The storage capacitor (first gate electrode and first metal pattern) serves as a local energy buffer or a timing element for an integrated oscillator, depending on the sensor type. The second TFT acts as an analog-to-digital converter or a data serializer. The connection member routes data from these local sensor nodes to a central, on-substrate edge microcontroller unit (MCU) with low-power wireless communication modules (e.g., Wi-Fi HaLow, LoRa). The MCU performs initial data aggregation, filtering, and local anomaly detection before securely transmitting compressed data to a cloud platform, reducing bandwidth and latency.
graph TD A[Substrate] --> B{First Insulating Layer}; B --> C1[First Channel Region (Sensor Transducer TFT)]; B --> D1[First Gate Electrode (Sensor Interface)]; D1 -- integrated with --> E[Environmental Sensor (CO2/Humidity)]; D1 --> F{Second Insulating Layer}; F --> G[First Metal Pattern (Capacitor/Bias)]; G --> H{Third Insulating Layer}; H --> I[Connection Member]; I --> J[Second TFT (ADC/Serializer)]; I --> K[On-Substrate Edge MCU]; K --> L[Wireless Comm. Module (Wi-Fi HaLow)]; subgraph IoT Sensor Matrix with Edge Computing E -- feeds data --> D1; J --> K; K -- processes --> M[Aggregated & Filtered Data]; M --> L -- transmits to --> N[Cloud Platform]; end
5. The "Inverse" or Failure Mode
Derivative 1.9: Self-Healing Dielectric Capacitor Array for Enhanced Durability
- Enabling Description: The second insulating layer, forming the dielectric of the storage capacitor (between the first gate electrode and first metal pattern), is engineered as a self-healing polymer composite. This composite incorporates microcapsules filled with a polymerizing healing agent (e.g., dicyclopentadiene monomer) and a dispersed catalyst (e.g., Grubbs' catalyst). In the event of a dielectric breakdown or minor crack formation due to mechanical stress or electrical overstress, the microcapsules rupture, releasing the healing agent into the damaged region. The healing agent then polymerizes upon contact with the catalyst, effectively repairing the dielectric and restoring the capacitor's functionality and capacitance stability. The connection member ensures continued electrical contact, and the first and third insulating layers can be conventional materials, offering a multi-layered self-healing architecture.
graph TD A[Substrate] --> B{First Insulating Layer}; B --> D1[First Gate Electrode]; D1 --> E{Second Insulating Layer (Self-Healing Polymer Dielectric)}; E --> F[First Metal Pattern]; F --> G{Third Insulating Layer}; G --> H[Connection Member]; subgraph Self-Healing Capacitor Array D1 -- Dielectric --> F; E -- localized damage --> I[Microcapsule Rupture]; I --> J[Healing Agent Release]; J -- polymerization --> K[Dielectric Repair]; K --> L[Restored Capacitance]; end
Derivative 1.10: Diagnosable Low-Power "Guardian" Mode for System Integrity
- Enabling Description: The TFT array substrate features a "Guardian Mode" for maintaining system integrity and minimal functionality during prolonged standby or fault conditions. In this mode, the first TFTs (driving TFTs) and their associated display elements are globally de-energized, drawing minimal leakage current. However, dedicated low-power diagnostic circuits, utilizing the second TFTs and the connection member, remain active. These circuits are designed to periodically sample critical parameters, such as the voltage retained on the first gate electrode (lower capacitor plate), leakage currents across insulating layers, or specific fault indicators. This data is processed by an ultra-low power microcontroller (on-substrate or external) to detect potential component degradation or impending failures without fully activating the display. This mode allows for proactive fault detection, essential for applications requiring high reliability and extended operational life, while significantly conserving power.
graph TD A[TFT Array Substrate] --> B[First TFT (Driving TFT) - De-energized]; A --> C[Storage Capacitor]; A --> D[Second TFT (Diagnostic/Monitoring)]; A --> E[Main Display Controller - Inactive]; D -- samples --> C[Voltage on First Gate Electrode]; D --> F[Connection Member]; F --> G[Ultra-low Power Microcontroller]; G -- processes --> H[Diagnostic Data]; subgraph Guardian Mode B -- global deactivation --> I[Extreme Power Saving]; D -- active --> J[Continuous System Health Check]; G -- outputs --> K[Fault Alerts/Status]; end
Derivatives for Claim 22: Connection Member Overlapping First Channel Region
Claim 22: A thin film transistor (TFT) array substrate comprising: a substrate; a first thin film transistor including a first channel region and a first gate electrode overlapping the first channel region, the first gate electrode and the first channel region being spaced apart from each other with a first insulating layer therebetween; a second thin film transistor including a second channel region and a second gate electrode overlapping the second channel region, the second gate electrode and the second channel region being spaced apart from each other with the first insulating layer therebetween; a second insulating layer disposed on the first and second gate electrode; a first metal pattern overlapping the first gate electrode, the first metal pattern and the first gate electrode being spaced apart from each other with the second insulating layer therebetween; a third insulating layer disposed on the first metal pattern; and a connection member disposed on the third insulating layer and electrically connecting the first gate electrode and the second thin film transistor, the connection member overlapping a portion of the first channel region in a plan view.
1. Material & Component Substitution
Derivative 2.1: Multi-Layered Graphene Channel TFT with Vertical Interconnects for Compactness
- Enabling Description: The first and second channel regions for the TFTs are fabricated using multi-layered graphene, deposited via chemical vapor deposition (CVD) onto a SiO2/Si substrate. Graphene's atomic thickness and high carrier mobility enable exceptionally compact device footprints. The connection member, which specifically overlaps a portion of the first channel region (of the first TFT) in a plan view, utilizes a Through-Insulator Via (TIV) or Through-Channel Via (TCV) structure. This involves etching a high aspect ratio via through the insulating layers and potentially a portion of the channel itself, followed by metallic filling (e.g., Tungsten) to establish direct vertical electrical contact. This vertical interconnect strategy, combined with graphene channels, drastically minimizes the lateral routing area required, enhancing pixel density. The insulating layers are composed of hexagonal boron nitride (hBN) for excellent dielectric properties and ALD HfO2 for the gate dielectric.
graph TD A[Substrate] --> B{First Insulating Layer (hBN)}; B --> C1[Graphene First Channel Region]; B --> C2[Graphene Second Channel Region]; B --> D1[First Gate Electrode]; D1 -- overlaps --> C1; D1 & D2 --> E{Second Insulating Layer (ALD HfO2)}; E --> F[First Metal Pattern]; F -- overlaps --> D1; F --> G{Third Insulating Layer (hBN)}; G --> H[Connection Member (Vertical Interconnect)]; H -- overlaps --> C1[Portion of Graphene First Channel Region]; H -- connects --> D1; H -- connects --> C2; subgraph Graphene TFT with Vertical Interconnect C1 & C2 -- High Mobility --> I[Ultra-Compact Layout]; H -- TIV/TCV --> J[Minimised Footprint & Parasitics]; end
Derivative 2.2: Organic TFTs (OTFTs) on Bio-degradable Substrate for Transient Electronics
- Enabling Description: The substrate is a bio-degradable polymer film, such as a polylactic acid (PLA) or regenerated cellulose derivative, for transient electronic applications (e.g., disposable sensors, eco-friendly smart packaging). The first and second TFTs employ organic semiconductor materials (e.g., poly(3-hexylthiophene) (P3HT) or TIPS-pentacene) for their channel regions, deposited using solution-based printing techniques like inkjet or gravure printing. The first and second gate electrodes, along with the first metal pattern (capacitor plates), are formed from conductive polymers (e.g., PEDOT:PSS) or flexible metallic inks (e.g., silver nanoparticle inks). Insulating layers are bio-degradable dielectrics, such as cross-linked polyvinylphenol (PVP) or a gelatin-based polymer. The connection member, also using conductive polymer tracks, is precisely patterned to overlap a portion of the organic first channel region, maintaining the compact pixel footprint and enabling a fully bio-degradable device.
graph TD A[Bio-degradable Substrate (PLA)] --> B{First Insulating Layer (PVP)}; B --> C1[Organic First Channel Region (P3HT)]; B --> C2[Organic Second Channel Region]; B --> D1[First Gate Electrode (PEDOT:PSS)]; D1 -- overlaps --> C1; D1 & D2 --> E{Second Insulating Layer (Gelatin)}; E --> F[First Metal Pattern (Conductive Ink)]; F -- overlaps --> D1; F --> G{Third Insulating Layer (PVP)}; G --> H[Connection Member (Conductive Polymer)]; H -- overlaps --> C1[Portion of Organic First Channel Region]; H -- connects --> D1; H -- connects --> C2; subgraph Bio-degradable OTFT Array A & B & C1 & D1 & E & F & G & H -- Bio-degradable --> I[Transient/Eco-friendly]; end
2. Operational Parameter Expansion
Derivative 2.3: Terahertz (THz) Modulator Array with Integrated Waveguide for High-Speed Imaging
- Enabling Description: The TFT array substrate is adapted as a pixelated Terahertz (THz) modulator array for high-speed THz imaging or spectroscopic applications. The first TFT's channel region is composed of a material (e.g., highly doped silicon, graphene, or VO2) whose THz conductivity can be strongly modulated by the electric field from the first gate electrode. The connection member, critical for this derivative, is designed not only to overlap a portion of the first channel region but also functions as an integral part of a localized THz waveguide or a resonant antenna structure. This structure guides the incident THz radiation and enhances its interaction with the modulated channel, enabling efficient THz amplitude or phase modulation. The storage capacitor (first gate electrode and first metal pattern) provides the necessary bias and control voltages for the THz modulation. Insulating layers are chosen for low dielectric loss at THz frequencies (e.g., benzocyclobutene (BCB) polymer or fused silica).
graph TD A[Substrate (Fused Silica)] --> B{First Insulating Layer (BCB)}; B --> C1[THz-Interacting First Channel Region (Doped Si)]; B --> D1[First Gate Electrode (Control)]; D1 -- overlaps --> C1; D1 & D2 --> E{Second Insulating Layer (BCB)}; E --> F[First Metal Pattern (THz Resonator/Bias)]; F -- overlaps --> D1; F --> G{Third Insulating Layer (BCB)}; G --> H[Connection Member (THz Waveguide/Antenna)]; H -- overlaps --> C1[Portion of THz-Interacting First Channel Region]; H -- connects --> D1; H -- connects --> C2[Second TFT (THz Driver)]; subgraph THz Modulator Array C1 -- modulates --> I[THz Radiation Properties]; H -- enhances interaction --> I; D1 & F -- control --> I; end
Derivative 2.4: Ultra-High Vacuum (UHV) Compatible TFT Array for Scientific Instrumentation
- Enabling Description: The TFT array substrate is meticulously designed for stable and reliable operation in Ultra-High Vacuum (UHV) environments (e.g., 10^-9 Torr or less), critical for advanced scientific instrumentation or specialized manufacturing processes. The substrate is UHV-grade single-crystal silicon. All materials comprising the semiconductor layers (silicon), insulating layers (thermally grown SiO2, sputtered Al2O3), and metallic patterns (Titanium/Platinum/Gold (Ti/Pt/Au) or Tungsten (W)) are selected for extremely low vapor pressure and minimal outgassing. The compact layout facilitated by the connection member overlapping the first channel region is crucial, as it minimizes the total surface area and internal volumes where gas molecules could be trapped and slowly released. All fabrication steps include rigorous cleaning protocols and annealing in UHV-compatible furnaces to eliminate residual contaminants.
graph TD A[UHV-Grade Silicon Substrate] --> B{First Insulating Layer (Thermally Grown SiO2)}; B --> C1[First Channel Region (Si)]; B --> D1[First Gate Electrode (W)]; D1 -- overlaps --> C1; D1 & D2 --> E{Second Insulating Layer (Sputtered Al2O3)}; E --> F[First Metal Pattern (W)]; F -- overlaps --> D1; F --> G{Third Insulating Layer (Thermally Grown SiO2)}; G --> H[Connection Member (Ti/Pt/Au)]; H -- overlaps --> C1[Portion of First Channel Region]; H -- connects --> D1; H -- connects --> C2[Second TFT (UHV Compatible)]; subgraph UHV TFT Array A & B & C1 & D1 & E & F & G & H -- UHV Compatible Materials & Processes --> I[Minimal Outgassing & Contamination]; H -- Compact Layout --> J[Reduced Surface Area]; end
3. Cross-Domain Application
Derivative 2.5: Integrated Neuromorphic Synapse Array for Edge AI Processors
- Enabling Description: The TFT array is repurposed as a dense neuromorphic synapse array, forming the core of an energy-efficient edge AI processor. The first TFT functions as a "synaptic transistor" whose channel conductance (representing a synaptic weight) is analog-programmable and non-volatile. This is achieved by integrating a memristive device directly within or adjacent to the first channel region. The storage capacitor (first gate electrode and first metal pattern) acts as a local analog memory element, storing the synaptic weight as a charge quantity on the first gate electrode, thereby modulating the first TFT's channel. The connection member, critically overlapping a portion of the first channel region, routes analog input "spike" signals to the first TFT and facilitates efficient read/write operations for updating the synaptic weights. The second TFT acts as a neuron activation function or an input multiplexer. The compact overlap design is essential for achieving high synapse densities required for neuromorphic computing.
graph TD A[Substrate] --> B{First Insulating Layer}; B --> C1[First Channel Region (Synaptic TFT with Memristor)]; B --> D1[First Gate Electrode (Synaptic Weight Storage)]; D1 -- overlaps --> C1; D1 & D2 --> E{Second Insulating Layer}; E --> F[First Metal Pattern (Control Electrode)]; F -- overlaps --> D1; F --> G{Third Insulating Layer}; G --> H[Connection Member]; H -- overlaps --> C1[Portion of Synaptic TFT Channel]; H -- connects --> D1; H -- connects --> C2[Second TFT (Neuron Activation/Mux)]; subgraph Neuromorphic Synapse Array C1 -- implements --> I[Analog Synaptic Weight]; D1 & F -- store --> J[Non-Volatile Weight]; H -- routes --> K[Input Signals & Weight Updates]; C2 -- processes --> L[Neuron Output]; end
Derivative 2.6: Space-Hardened Radiation Detector Matrix with Integrated Readout
- Enabling Description: The TFT array is transformed into a robust, space-hardened matrix of radiation detectors for cosmic ray detection or particle physics experiments. The first channel region is composed of a radiation-sensitive material, such as amorphous silicon (a-Si:H) or a direct conversion material like Cadmium Telluride (CdTe), which generates charge upon interaction with high-energy particles. The first TFT functions as a low-noise charge amplifier for the detected signal. The storage capacitor (first gate electrode and first metal pattern) serves as a charge integration element for the amplified signal. The connection member, which overlaps a portion of the radiation-sensitive first channel region, is fabricated with radiation-hardened metallization (e.g., a thick gold (Au) or platinum (Pt) layer) and employs shielded routing to minimize single-event upsets (SEUs) and total ionizing dose (TID) effects. The second TFT functions as a reset or bias control transistor. The compact overlap design maximizes the fill factor of the radiation-sensitive area.
graph TD A[Substrate (Radiation-Hardened Si)] --> B{First Insulating Layer}; B --> C1[Radiation Sensitive First Channel Region]; B --> D1[First Gate Electrode]; D1 -- overlaps --> C1; D1 & D2 --> E{Second Insulating Layer (Radiation-Hardened Dielectric)}; E --> F[First Metal Pattern]; F -- overlaps --> D1; F --> G{Third Insulating Layer (Radiation-Hardened Dielectric)}; G --> H[Connection Member (Radiation-Hardened Metal)]; H -- overlaps --> C1[Portion of Radiation Sensitive Channel Region]; H -- connects --> D1; H -- connects --> C2[Second TFT (Bias/Reset)]; subgraph Space Radiation Detector C1 -- detects --> I[Incident Radiation]; C1 -- amplified by --> J[First TFT (Charge Amplifier)]; D1 & F -- integrates --> K[Charge Signal]; H -- routes --> L[Radiation-Hardened Readout]; end
4. Integration with Emerging Tech
Derivative 2.7: Machine Learning Inference Engine on Array Substrate with Resistive Memory
- Enabling Description: The TFT array substrate is re-engineered as a hardware accelerator for machine learning (ML) inference, integrating resistive random-access memory (RRAM) elements. The first channel region of the first TFT is formed in series with, or directly incorporates, an RRAM device (e.g., using TaOx or HfOx as the switching material). The first gate electrode and first metal pattern (capacitor) provide the precise voltage pulses for programming and reading the RRAM's resistance state, which represents a synaptic weight. The connection member, specifically designed to overlap a portion of the first channel region and RRAM device, routes analog input signals directly to the input of this combined TFT-RRAM element. The second TFT acts as an analog activation function (e.g., ReLU or Sigmoid approximation) or a current-to-voltage converter. This enables highly parallel, in-memory computing for efficient ML inference at the edge, leveraging the compact layout for dense weight matrices.
graph TD A[Substrate] --> B{First Insulating Layer}; B --> C1[First Channel Region (TFT with RRAM)]; B --> D1[First Gate Electrode (RRAM Program/Read)]; D1 -- overlaps --> C1; D1 & D2 --> E{Second Insulating Layer}; E --> F[First Metal Pattern (RRAM Bias)]; F -- overlaps --> D1; F --> G{Third Insulating Layer}; G --> H[Connection Member]; H -- overlaps --> C1[Portion of TFT/RRAM Channel]; H -- connects --> D1; H -- connects --> C2[Second TFT (Activation/I-V Conv)]; subgraph ML Inference Engine with RRAM C1 -- implements --> I[Synaptic Weight (RRAM)]; H -- routes --> J[Analog Input Signals]; D1 & F -- program/read --> I; C2 -- processes --> K[Inference Output]; end
Derivative 2.8: Real-Time Performance Monitoring with Blockchain Identity and Provenance
- Enabling Description: Each TFT array substrate integrates unique Physical Unclonable Function (PUF) elements, generated from inherent, uncontrollable manufacturing variations in the first channel region's physical or electrical characteristics (e.g., random dopant fluctuations, grain boundary distribution). This PUF generates a cryptographic digital fingerprint for the substrate. The connection member, intentionally designed to overlap a portion of this PUF-generating first channel region, provides electrical access for robust, low-power readout of the PUF. Concurrently, performance data (e.g., threshold voltage drift of the first TFT, capacitance degradation of the storage capacitor) is continuously measured by the second TFT acting as a local sensor interface. This performance data, along with the PUF-generated immutable identity, is timestamped, cryptographically signed, and periodically uploaded to a distributed ledger (blockchain) for real-time, tamper-proof provenance and performance tracking throughout the product lifecycle, enhancing supply chain security and authenticated operational history.
graph TD A[TFT Array Substrate] --> B[First TFT]; A --> C[Storage Capacitor]; B -- generates --> D[PUF Element (Physical Unclonable Function)]; D -- derived from --> E[First Channel Region Variations]; B -- monitors --> F[Performance Data (Vth, Cst)]; F --> G[Second TFT (Sensor Interface)]; G --> H[Connection Member]; H -- overlaps --> D[Portion of First Channel Region]; H -- transmits --> I[PUF ID + Performance Data]; I --> J[Cryptographic Module]; J -- signs --> K[Authenticated Data Packet]; K --> L[Blockchain Network]; subgraph Blockchain Identity & Provenance D -- unique & immutable --> M[Digital Fingerprint]; I -- real-time tracking --> N[Lifecycle History]; end
5. The "Inverse" or Failure Mode
Derivative 2.9: Graceful Degradation Mode with Fault-Tolerant Redundancy in Channel Layer
- Enabling Description: The TFT array substrate is designed with localized, fine-grained redundancy within the first channel region to enable graceful degradation upon localized failure. Each "first channel region" is segmented into multiple sub-regions, with only one active at any given time. The connection member, overlapping a portion of this segmented first channel region, includes a micro-reconfigurable interconnect matrix (e.g., using laser-fusible links or non-volatile switches). In the event a primary active channel segment or the associated first TFT is detected as faulty (e.g., by a change in source-drain current characteristics), an on-substrate control logic (potentially utilizing the second TFT as a fault detection and reconfiguration controller) can reconfigure the connection member's interconnects to bypass the faulty segment and activate a redundant, adjacent channel segment. This ensures continued operation with minimal loss of performance, preventing a complete pixel blackout and improving overall display reliability.
graph TD A[TFT Array Substrate] --> B[Primary First TFT/Capacitor]; A --> C[Redundant First TFT/Capacitor Elements]; B -- contains --> D[Segmented First Channel Region (Primary)]; C -- contains --> E[Segmented First Channel Region (Redundant)]; F[Connection Member] -- overlaps --> D; F -- includes --> G{Reconfigurable Interconnect Matrix}; G -- routes --> H[Signal Path]; I[Fault Detection Logic (via Second TFT)] -- detects --> J[Fault in Primary Channel Segment]; J --> G[Reconfigures]; G -- reroutes --> K[Signal to Redundant Channel Segment]; subgraph Fault-Tolerant Redundancy D & E -- Segmentation --> L[Localized Fault Handling]; G -- Reconfiguration --> M[Graceful Degradation]; end
Derivative 2.10: Environmental Feedback-Induced Hibernation Mode with Contextual Awareness
- Enabling Description: The TFT array substrate integrates multiple ambient environmental sensors (e.g., light, proximity, temperature, accelerometer) directly onto the substrate. The first TFT's channel region is designed to have tunable sensitivity to one of these parameters, providing a contextually aware trigger. The storage capacitor (first gate electrode and first metal pattern) stores a dynamically adjustable environmental threshold profile. When the aggregated environmental data indicates specific conditions (e.g., dark, no motion, low temperature), the second TFT (acting as a multi-modal control gate) triggers a sophisticated "Hibernation Mode." In this mode, the connection member, which overlaps a portion of the first channel region, selectively powers down or puts the first TFT and related display elements into an ultra-low power state, retaining critical data in the capacitor but suspending active display operation. The contextual awareness prevents unnecessary activation and optimizes power consumption significantly.
graph TD A[TFT Array Substrate] --> B[First TFT]; A --> C[Storage Capacitor]; A --> D[Multi-modal Environmental Sensors]; B -- tunable sensitivity to --> D; C -- stores --> E[Dynamic Environmental Threshold Profile]; D -- provides --> F[Real-time Environmental Data]; F -- compared with --> E; G[Second TFT (Multi-modal Control Gate)] -- triggers --> H[Contextual Hibernation Mode]; I[Connection Member] -- overlaps --> B[Portion of First Channel Region]; I -- in hibernation mode --> J[Selective Power Down/Ultra-Low Power State]; subgraph Contextual Hibernation D --> G; E --> G; H --> J; J --> K[Optimized Power Savings & Longevity]; end
Combination Prior Art Scenarios with Open-Source Standards
These scenarios illustrate how the core concepts of US Patent 10720483 (stable capacitor structure, TFT array, pixel control) can be combined with existing open-source standards to yield obvious prior art disclosures.
Combination with RISC-V Microcontroller Core (ISA) for On-Panel Processing:
- Scenario: Integrate a low-power, open-source RISC-V microcontroller (MCU) core, such as the PicoRV32 (available under the permissive MIT license), directly onto the display array substrate. This MCU would be implemented using the same thin-film transistor (TFT) technology as the pixel array itself, either amorphous silicon (a-Si), polysilicon (poly-Si), or Indium Gallium Zinc Oxide (IGZO) TFTs. The RISC-V MCU would be strategically placed in the display's non-display area or integrated into the gate/source driver peripheral logic.
- Enabling Description: The RISC-V MCU core on the display substrate, utilizing TFTs, is tasked with managing pixel-level compensation and diagnostic routines. It reads pixel performance data (e.g., threshold voltage variations of the driving TFTs (first TFTs), actual capacitance values of the storage capacitors (first gate electrode and first metal pattern)) via dedicated sensing TFTs (second TFTs) and the connection members. Based on this data and firmware implementing open-source algorithms, the RISC-V MCU calculates and applies dynamic compensation values to the pixel drive signals, enhancing display uniformity and mitigating artifacts caused by manufacturing variations or aging. The stable capacitance of the storage capacitors, as enabled by the electrode overlap and opening design of US10720483, is crucial for accurate and reliable pixel state retention during these compensation cycles. Communication between the RISC-V core and the main display controller can occur via a simple, open-standard serial interface (e.g., SPI) also implemented with TFTs.
- Relevance: This combination demonstrates that leveraging an open-source processor instruction set architecture (ISA) with the patent's stable TFT-capacitor pixel array enables advanced, distributed intelligence directly on the display panel, which would be an obvious architectural improvement for managing display quality.
Combination with Open-Source Display Protocols (e.g., MIPI DSI Physical Layer) for Integrated Interface:
- Scenario: Implement the physical layer and timing controller for an open-source display interface protocol, such as a subset of the MIPI DSI (Display Serial Interface) standard, using the same TFT array substrate manufacturing processes.
- Enabling Description: High-speed data receivers, including deserializers and clock data recovery (CDR) circuits for MIPI DSI (which has publicly available specifications for its C-PHY/D-PHY physical layers), are designed and integrated into the gate driver and source driver integrated circuits located on the display's border. These circuits are fabricated using high-performance polysilicon (poly-Si) or IGZO TFTs, capable of operating at frequencies required by the MIPI DSI standard. The logic for pixel data decoding and distribution, as defined by the MIPI DSI protocol, is implemented using the array's TFTs. The critical aspect of the storage capacitor (first gate electrode and first metal pattern) from US10720483, with its inherent stability against overlay deviation, is essential for accurately retaining the pixel data after deserialization and during display refresh. The connection member's design and the robust insulating layers ensure reliable, high-integrity signal transmission for the decoded data and driving voltages across the array, adhering to the stringent timing requirements of MIPI DSI.
- Relevance: This demonstrates that integrating open-source display interface standards directly onto the display substrate, utilizing the patent's core (stable pixel drive, robust connection), is an obvious step for reducing component count, simplifying manufacturing, and creating industry-standard compliant displays.
Combination with Open-Source Real-Time Operating Systems (RTOS) on Embedded Microcontrollers for Localized Control:
- Scenario: An array of embedded microcontrollers (MCUs), implemented using the TFT fabrication process, runs an open-source Real-Time Operating System (RTOS) such as FreeRTOS (MIT license) or Zephyr RTOS (Apache 2.0 license) to manage localized display functions or integrate small-scale sensor networks.
- Enabling Description: Small, dedicated microcontrollers (MCUs), each responsible for controlling a specific block of pixels or a local sensor cluster on the display array substrate, are implemented using TFTs. These MCUs run a lightweight open-source RTOS, enabling deterministic task scheduling for display refresh, responding to sensor inputs (if the array is also repurposed for sensing, as in derivatives 1.5 or 1.8), and managing communication with a main host processor. The stable storage capacitor (first gate electrode and first metal pattern) in each pixel, as described in US10720483, is fundamental for accurate pixel state retention and consistent RTOS operation. The compact connection member design, especially where it overlaps channel regions (as in Claim 22 and its derivatives), enables high-density integration of these MCUs and their associated local memory. The RTOS facilitates precise, real-time control over display timing and allows for distributed, intelligent processing capabilities across the panel.
- Relevance: This combination highlights how the patent's reliable and compact pixel structure provides a suitable hardware platform for deploying open-source RTOS-driven embedded intelligence, creating display arrays with enhanced autonomy and programmability beyond traditional display drivers.
Generated 5/28/2026, 1:56:42 PM