Obviousness

An analysis of the obviousness of U.S. Patent No. 10,651,866 ("the '866 patent") under 35 U.S.C. § 103 suggests that its claims may be vulnerable to an obviousness challenge, particularly when considering the combination of prior art references cited during its prosecution. The legal standard for obviousness requires determining whether the differences between the claimed invention and the prior art are such that the invention as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art (PHOSITA).

A PHOSITA in this context would be an electrical engineer or a related professional with experience in digital signal processing (DSP), specifically in audio applications, analog-to-digital conversion, and microphone array systems. Such a person would be familiar with oversampling techniques like Pulse Density Modulation (PDM), decimation filters (e.g., CIC filters), and the principles of delay-and-sum beamforming.

Obviousness Analysis Based on Prior Art Combinations

The primary argument for the obviousness of the '866 patent's claims rests on the combination of U.S. Patent Application Publication No. 2011/0211718 A1 (Gieske et al.) and U.S. Patent No. 7,242,773 B2 (Feng et al.).

Primary Combination: Gieske et al. in view of Feng et al.

• Independent Claims 1 and 12: These claims broadly cover a system and method for receiving an oversampled digital signal from a sensor, applying a time delay to this oversampled signal, and then decimating and filtering it to a baseband rate.
• Gieske et al. Contribution: As noted in the prior art analysis, Gieske et al. is highly relevant because it explicitly teaches the core concept of implementing a fractional delay for beamforming directly on a Pulse Density Modulated (PDM) signal, which is a one-bit oversampled signal. This directly addresses the fundamental inventive concept of the '866 patent.
• Feng et al. Contribution: Feng et al. provides a detailed, conventional architecture for a PDM receiver module, which is the exact environment in which the '866 invention operates. Feng describes the standard stages of such a receiver, including the use of cascaded-integrator-comb (CIC) filters followed by other decimation and filtering stages to convert the oversampled PDM signal into a baseband PCM signal.
• Motivation to Combine: A PHOSITA, seeking to implement the fractional delay beamforming system for PDM microphones taught by Gieske et al., would naturally turn to a standard PDM receiver architecture like that detailed in Feng et al. Gieske teaches what to do (delay the PDM stream), and Feng teaches where to do it by laying out the standard signal processing path.

The '866 patent elaborates on placing the time delay element at various points within the oversampled domain: either before the PDM receiver module (FIG. 2C, element 276) or between the different decimation and filtering stages within the receiver (FIGS. 4, 5, 6, and 7). A PHOSITA would recognize that placing the delay element at any point before the final decimation to the baseband rate would still be in the "oversampled domain." The decision of where precisely to place this delay element would be a matter of routine engineering optimization, not invention.

For instance, placing the delay buffer at the highest sampling rate (before any filtering, as in FIG. 3) would provide the finest time resolution, as described in the '866 patent. Placing it after the first decimation stage (e.g., after the CIC filter, as in FIG. 5) would reduce the size of the required buffer at the cost of slightly coarser time resolution. These are predictable design trade-offs that a skilled engineer would evaluate based on system constraints like required precision, memory availability, and processing power. Therefore, exploring these different implementation points as shown in the '866 patent would have been an obvious design choice when combining the teachings of Gieske et al. and Feng et al.

Analysis of Dependent Claims

Many of the dependent claims of the '866 patent add further conventional details that would not overcome an obviousness rejection based on this combination.

• Programmable Delay (Claim 3): The concept of making a delay programmable for a beamforming application is inherent to "steering" the beam. As described in U.S. patents like Chabanne et al. (US 9,661,400 B2) and Choi et al. (US 8,958,582 B2), adjusting delays to change the directional focus of a microphone array is a fundamental aspect of beamforming. A PHOSITA implementing Gieske et al.'s delay would be motivated to make it programmable to create a steerable beam, a well-known goal in the art.
• Specific Filter Architectures (Claims 4, 5, 6): Claiming the use of a CIC filter, half-band filters, or a multi-stage architecture for the PDM receiver module merely recites the standard components of such a system, as explicitly taught by Feng et al. These elements are part of the known environment and do not add a non-obvious element to the claimed combination.
• Application to Beamforming (Claims 9-11, 15-18): These claims explicitly apply the time-delay method to a beamforming system with multiple microphones. This is the primary motivation disclosed by Gieske et al. and is the general context of Chabanne et al. and Choi et al. Combining the teachings would inherently lead to a beamforming application. The use of an arithmetic block to sum or subtract the delayed signals (FIG. 10) is the standard final step in any delay-and-sum beamformer.

Conclusion

A strong argument exists that the claims of U.S. Patent 10,651,866 would have been obvious to a person of ordinary skill in the art. The primary reference, Gieske et al., teaches the core concept of applying a fractional delay to an oversampled PDM signal for beamforming. Feng et al. teaches the conventional multi-stage architecture of the PDM receiver where this delay would be implemented. The motivation to combine these references would be to implement Gieske's concept using a standard, well-understood PDM receiver design as shown by Feng. The specific placement of the delay element within the oversampled processing chain, as detailed in the '866 patent, represents a set of predictable and obvious design choices for a skilled engineer seeking to optimize performance and resource usage. Additional features, such as programmability and the use of standard filter types, are also well-documented in the prior art and would be considered obvious additions to the core concept.