Obviousness — US Patent 10468543

Obviousness Analysis of U.S. Patent No. 10,468,543

To: In-House Counsel
From: Senior Patent Analyst
Date: May 14, 2026
Subject: Analysis of Obviousness for U.S. Patent No. 10,468,543 in view of cited prior art.

1. Introduction and Conclusion

This report provides an analysis of the patentability of U.S. Patent No. 10,468,543 ("the '543 patent") in view of prior art references. The '543 patent claims a microstructure-enhanced photodetector (MSPD), which may be an avalanche photodiode (MSAPD), monolithically integrated with active electronic circuitry on a single chip. The key feature is the use of intentionally formed microstructures, such as holes, to enhance light absorption and quantum efficiency, particularly for high-speed applications in materials like Silicon (Si) or Silicon-Germanium (SiGe).

Based on the analysis of the prior art provided, it is my professional opinion that a person of ordinary skill in the art (POSITA) at the time of the invention would have found the claims of the '543 patent to be obvious. Specifically, combining the teachings of Choe et al. (U.S. Patent No. 9,590,060), which discloses micro-patterned photodetectors for enhanced quantum efficiency in a CMOS image sensor, with Gothoskar et al. (U.S. Patent No. 7,354,790), which explicitly teaches the monolithic integration of high-speed SiGe PIN photodiodes with transimpedance amplifiers (TIAs), would render the invention claimed in the '543 patent obvious.

2. Understanding of a Person of Ordinary Skill in the Art (POSITA)

A Person of Ordinary Skill in the Art (POSITA) at the time of the invention (around the 2013-2014 priority date) would have a Master's degree or Ph.D. in Electrical Engineering, Applied Physics, or a related field, with several years of experience in semiconductor device physics, optoelectronics, and CMOS/BiCMOS fabrication processes. This person would be familiar with the design of photodiodes (PIN and APD), the challenges of light absorption in silicon at near-infrared wavelengths, and standard techniques for integrating photodetectors with electronic circuits on a single chip.

3. Analysis of Obviousness for Key Claims

The primary inventive concept of the '543 patent is the combination of two known concepts: (1) using surface microstructures to enhance light absorption in a photodetector, and (2) monolithically integrating that photodetector with its associated processing electronics (like a TIA) on a single silicon substrate. The prior art demonstrates that both of these concepts were well-known.

Ground 1: Obviousness of Independent Claim 1 over Choe et al. in view of Gothoskar et al.

Independent Claim 1 recites:

A single-chip device comprising:
- A microstructure-enhanced photodetector (MSPD) on a substrate, itself comprising:
  - An intermediate layer, a first layer, and a second layer of Si, Ge, or SiGe.
  - At least one of these layers has intentionally formed "holes" transverse to the layers.
  - The first and second layers are doped, and the intermediate layer is less doped (forming a PIN or NIP structure).
  - An input portion to receive an optical input.
  - An output portion to provide an electrical output.
- An active electronic circuit on the same substrate to process the MSPD's electrical output.
- A communication channel between the MSPD and the circuit.

Analysis:

Choe et al. (US 9,590,060) discloses a CMOS image sensor, which is inherently a single-chip device containing an array of photodetectors monolithically integrated with active electronic circuitry (CMOS logic for pixel readout and signal processing). Choe’s photodetectors are fabricated in a silicon substrate and consist of doped regions forming a photodiode (a P-N or PIN-like structure). Crucially, Choe teaches forming a "light-blocking pattern" with openings (i.e., "holes") on the light-receiving surface to create a diffraction grating. The explicit purpose is to increase the optical path length, thereby enhancing light absorption and quantum efficiency (Choe, col. 2, ll. 55-67). This structure directly reads on the "microstructure-enhanced photodetector" limitation of claim 1.
Gothoskar et al. (US 7,354,790) addresses a known problem in the field: the need for high-speed, low-cost optical receivers. Gothoskar's solution is the monolithic integration of a high-speed photodetector with a transimpedance amplifier (TIA) on a single silicon substrate (Gothoskar, Abstract). It specifically teaches using SiGe for the absorption (intrinsic) layer to extend detection to longer wavelengths (1310-1550 nm), and it describes a PIN photodiode structure. The TIA is the specific type of "active electronic circuit" most commonly used to process the output of a high-speed photodiode.

Motivation to Combine:

A POSITA would have been motivated to combine the absorption-enhancement technique of Choe with the high-speed integrated photodetector/TIA architecture of Gothoskar for several reasons:

Improved Performance at Lower Cost: Gothoskar teaches that monolithic integration reduces packaging costs and parasitic capacitances, leading to higher performance. Choe teaches that microstructures improve quantum efficiency. A POSITA would recognize that applying Choe's efficiency-enhancing structures to Gothoskar's high-speed, integrated SiGe PIN photodiode would create a superior optical receiver. The goal would be to achieve the high efficiency of an InP-based detector (as mentioned in the '543 patent's background) but with the low-cost, monolithic integration benefits of a silicon/SiGe platform, as taught by Gothoskar.
Overcoming Known Limitations: The '543 patent itself acknowledges the trade-off between absorption (requiring a thick I-layer) and speed (requiring a thin I-layer) in silicon photodetectors. This was a well-known problem. A POSITA, aware of light-trapping techniques like those in Choe, would naturally look to apply them to the high-speed photodetectors of Gothoskar to increase absorption in a thin I-layer, thereby improving quantum efficiency without sacrificing bandwidth.
Predictable Result: The combination is a simple substitution of one known type of photodetector (Choe's micro-structured one) for another (Gothoskar's planar one) within an integrated circuit. The result—an integrated receiver with higher efficiency—would have been entirely predictable. The underlying fabrication processes (lithography, etching, deposition) are common to both references and are standard in CMOS manufacturing.

Therefore, claim 1 is rendered obvious by the combination of Choe and Gothoskar. This combination teaches a single-chip device with a microstructure-enhanced photodetector (from Choe) monolithically integrated with an active electronic circuit (a TIA, from Gothoskar), all on a silicon-based substrate. Dependent claims related to using SiGe (claim 15), specific circuit types like TIAs (claim 18), and the purpose of enhancing quantum efficiency (claim 22) are also rendered obvious by this combination.

Ground 2: Obviousness of Independent Claim 16 (Method Claim) over Choe et al. in view of Gothoskar et al.

Independent Claim 16 recites a method of making the device of claim 1, comprising the steps of:

Providing a substrate.
Forming top, bottom, and intermediate layers (doped/undoped/doped).
Intentionally forming holes in at least one layer.
Forming input and output portions.

Analysis:

The method steps recited in claim 16 are the necessary and conventional process steps required to fabricate the device of claim 1.

Choe et al. discloses the a method for fabricating its image sensor, which includes forming photodiodes (P-N junctions) in a substrate and patterning the surface to create the light-trapping structure (the "holes" or "openings").
Gothoskar et al. provides a detailed method for monolithically fabricating SiGe PIN photodiodes alongside CMOS transistors for the TIA, including steps for epitaxial growth of the detector layers.

A POSITA, motivated to create the combined device as discussed above, would have found it obvious to combine the fabrication steps from these references. This would involve using standard CMOS/BiCMOS process flows, as described in Gothoskar, and incorporating the patterning and etching steps for creating the microstructures, as taught by Choe. The result would be the method recited in claim 16.

4. Other Relevant Prior Art

Tanabe et al. (US 2009/0230491 A1): This reference further reinforces the obviousness argument. Tanabe explicitly teaches texturing ("concave-convex structure") the light-receiving surface of an integrated photodiode to reduce reflection and enhance light absorption. This provides another clear source for the "microstructure" or "hole" element of the claims. Combining Tanabe with Gothoskar leads to the same conclusion of obviousness.
Ahn et al. (U.S. 8,629,479 B2): While Ahn's "holes" function as light pipes through overlying layers rather than as absorption-enhancing structures within the semiconductor itself, it nonetheless teaches the fundamental concept of creating high-aspect-ratio holes in an integrated photodetector device on a single chip. This shows that the idea of perforating layers in a photodetector was known in the art.

5. Summary and Overall Conclusion

The '543 patent claims a combination of elements, each of which was well-known in the art prior to the invention. The concept of using surface texturing and microstructures to enhance light absorption in photodetectors was established (Choe, Tanabe). The concept of monolithically integrating high-speed Si/SiGe photodiodes with processing electronics like TIAs on a single chip was also well-established (Gothoskar). A person of ordinary skill in the art, seeking to improve the performance of integrated optical receivers, would have found it obvious to combine these known elements to achieve the predictable result of a higher-efficiency, high-speed, single-chip photodetector. Therefore, the claims of U.S. Patent No. 10,468,543 are likely invalid as obvious under 35 U.S.C. § 103.