Obviousness

To analyze the obviousness of US patent 10056902 under 35 U.S.C. § 103, we need to identify combinations of prior art references that predate the patent's priority date of June 2, 2006, and explain why a person having ordinary skill in the art (PHOSITA) would have been motivated to combine them to arrive at the claimed invention. The independent claims, Claim 1 (integrated circuit device) and Claim 11 (method of control), are the primary focus.

Elements of Independent Claims (Claims 1 and 11)

The core elements of the independent claims revolve around a memory control component (or method of controlling) that interacts with a DRAM and manages its on-die termination (ODT) during write operations. Key features include:

1. Memory Controller/IC Device: An integrated circuit device configured to control a DRAM.
2. Transmission of Commands: Transmitting a write command, a chip-select signal, and one or more commands to store a digital control value in a DRAM register.
3. Programmable Termination Impedance: The digital control value specifies a value of a termination impedance.
4. Conditional ODT Coupling: The DRAM couples this termination impedance to its data interface in response to the chip-select signal and the write command.
5. Timed ODT Application/Decoupling: The termination impedance is coupled to the data interface prior to the reception of write data (according to a predetermined time after the write command) and decoupled from the data interface after the reception of the write data.
6. Write Data Transmission: Transmitting the actual write data to the DRAM's data interface.

The patent itself describes a "prior-art memory system 100" in FIG. 1, which employs a single on-die termination scheme where the memory controller asserts a termination control signal for non-selected memory modules during write operations and deasserts it for the selected module. This background highlights the known concept of ODT and its control by a memory controller.

Identification of Prior Art References

Given the priority date of June 2, 2006, we look for prior art that teaches the elements of the claims, particularly programmable ODT, control via commands, and dynamic timing of ODT during write operations.

The search results provide excellent prior art, particularly regarding DDR2 and DDR3 SDRAM specifications and technical notes. The relevant publications and information include:

• DDR2 SDRAM Standard (JEDEC JESD79-2): Published in September 2003, this standard formalized the first commercial implementation of On-Die Termination (ODT).
• "New Function of DDR2 SDRAM - On Die Termination (ODT)" (Digchip): This technical note, though its specific publication date is listed as April 15, 2007, describes ODT as a feature added to DDR2 SDRAM, indicating it was understood and implemented prior to 2006. It explicitly states that DDR2 SDRAM embeds termination resistors, and the DRAM controller can use an ODT control pin to set the termination resistance (e.g., ON and OFF) and select impedance values (50Ω, 75Ω, 150Ω) via the Extended Mode Register Set (EMRS). It also discusses how ODT is used during write operations, where the DDR2 SDRAM (as the receiving end) has its ODT pin high to open the internal termination resistor.
• Micron Technology Technical Note TN-47-02 (referenced in Digchip's "TECHNICAL NOTE"): Discusses DDR2 features, including ODT. It mentions JEDEC identified ODT values of 75 ohms and 150 ohms, and later added 50 ohms as an optional support. It shows an "Extended Mode Register Control for On-Die Termination" in Figure 1.
• Micron Technology Technical Note TN-41-04: "DDR3 Dynamic On-Die Termination": While this document is dated March 2008, it explicitly discusses the new feature introduced with DDR3 as "dynamic on-die termination (ODT)" which "enables the DRAM to switch between HIGH or LOW termination impedance without issuing a mode register set (MRS) command." It states that if Rtt_Nom and Rtt_WR are enabled via the mode register, the DRAM changes termination from Rtt_Nom to Rtt_WR upon issuing the WRITE command, and back to Rtt_Nom when the WRITE burst is complete. This strongly suggests that dynamic ODT switching based on write commands and programmable values was a known concept or a natural evolution in DDR3, building upon DDR2 ODT.
• Wikipedia "On-die termination": States that ODT is controlled via a programmable configuration register in the DRAM by the DRAM controller. It further notes that ODT is turned on just before data transfer and shut off immediately after.
• Xilinx Answer Record 38623: "Why is ODT issued late by the MCB when operating in DDR2 mode 400 Mbps?" This document, while addressing a specific issue, confirms that in DDR2, the ODT pin goes high at the same time the WRITE command is issued to the DRAM, enabling termination 2nCK after the WRITE command. It also describes issues with ODT being enabled "too late" and solutions involving adjusting CAS latency to enable termination "one clock cycle before the first rising edge of DQS". This clearly demonstrates the understanding and practice of timing ODT assertion relative to write commands and data reception in DDR2.

Obviousness Analysis

Based on the identified prior art, the elements of Claims 1 and 11 appear to be individually known and the combination would have been obvious to a PHOSITA before June 2, 2006.

1. Memory Controller/IC Device and Transmission of Commands:
It was well-known in the art to have a memory controller (IC device) that transmits write commands and chip-select signals to a DRAM. The DDR2 SDRAM standard (published September 2003) formalized the use of ODT within DRAMs. Furthermore, the Digchip technical note on DDR2 SDRAM clearly states that the "DRAM controller can use ODT to set the termination resistance simultaneously to each pin...ON and OFF".

2. Programmable Termination Impedance via Register:
The prior art clearly teaches programmable ODT values stored in DRAM registers. The DDR2 standard allowed selection of impedance values like 50Ω, 75Ω, or 150Ω, set in advance via the Extended Mode Register Set (EMRS). The Wikipedia entry on ODT explicitly mentions that the "DRAM controller manages the on-die termination resistance through a programmable configuration register that resides in the DRAM" and that "in DRAM, it is done by setting up the device's extended mode register with the proper ODT value."

3. Conditional ODT Coupling in Response to Commands:
The DDR2 architecture already incorporated ODT that could be dynamically enabled/disabled. For example, during a write operation, the receiving DDR2 SDRAM enables ODT by asserting the ODT pin high. This shows that ODT was coupled in response to control signals (like the ODT pin, which would be controlled by the memory controller in conjunction with a write command and chip-select). The Xilinx Answer Record for DDR2 explicitly states that "the ODT pin will always go high at the same time that the WRITE command is issued to the DRAM". This directly links the ODT activation to the write command.

4. Timed ODT Application/Decoupling Relative to Write Data:
This is a critical aspect of the claims. The prior art demonstrates that ODT was understood to be dynamically turned on "just before the data transfer and then shut off immediately after". More specifically, in DDR2, the ODT pin goes high with the WRITE command, enabling termination a predetermined time (e.g., 2nCK) after the WRITE command. The Xilinx document even discusses the problem of ODT being enabled "too late" leading to overshoot, and suggests solutions to enable ODT "one clock cycle before the first rising edge of DQS" (which carries the write data). This unequivocally teaches the concept of coupling ODT prior to write data reception according to a predetermined time after the write command, and the need to decouple it after reception. The DDR3 dynamic ODT (TN-41-04), although technically after the priority date, describes a natural evolution where ODT changes from a nominal value to a write-specific value upon a WRITE command and reverts after the burst, "without having to issue additional MRS commands". This demonstrates the continuous development and understanding of dynamically timed ODT.

Motivation to Combine:

A PHOSITA in memory system design would have been motivated to combine these known elements for several reasons:

• Improved Signal Integrity: The primary motivation for ODT itself is to improve signal integrity by minimizing reflections, overshoot, and crosstalk in high-speed data transfers. As data rates increased (e.g., with DDR2 and DDR3), optimizing ODT became even more critical.
• System Performance and Reliability: By precisely controlling the timing of ODT application and removal, especially during write operations, designers could prevent signal degradation (e.g., overshoot mentioned in Xilinx Answer Record) and improve signaling margins, leading to more reliable data transfer and potentially higher operating frequencies.
• Flexibility and Optimization: The ability to program ODT values via mode registers (EMRS in DDR2) provided flexibility to tune the termination for different system configurations and operating conditions. Combining this programmability with dynamic, command-triggered timing would allow for optimal termination settings for specific transaction types (e.g., write operations) without constant re-configuration or sacrificing performance. The desire to "optimize termination values for different loading conditions" is explicitly stated in the context of dynamic ODT.
• Efficiency: Dynamically switching ODT (e.g., turning it on only when needed for write data reception and off afterwards) would reduce power consumption and improve bus scheduling, as noted in the DDR3 dynamic ODT technical note. The prior art already suggests disabling ODT during idle periods to save power. Extending this to precisely time ODT around the actual data transfer window during a write operation is a logical step.

Therefore, a PHOSITA, faced with the challenges of maintaining signal integrity and optimizing performance in high-speed DRAM systems (like DDR2 and the emerging DDR3), would have found it obvious to combine the known concepts of memory controllers, programmable ODT values set in DRAM registers via commands, and dynamic, command-triggered ODT timing (application before write data and removal after write data) to achieve the benefits of improved signal integrity, reliability, and efficiency.

For example, a PHOSITA combining the DDR2 SDRAM ODT implementation (programmable values via EMRS, ODT pin control by controller for write operations) with the common understanding that ODT should be "turned on just before the data transfer and then shut off immediately after", and further informed by issues of late ODT activation during DDR2 write cycles, would be motivated to develop a memory controller that transmits commands to set the ODT value in a register and then precisely times the ODT assertion and deassertion relative to the write command and subsequent data transfer.