Prior art

The most relevant prior art for US patent 10025731, titled "Memory module and circuit providing load isolation and noise reduction," includes patents and patent applications that predate its earliest priority date of April 14, 2008. These references address various aspects of memory module design, buffering, power management, and signal integrity. The distinct features of US10025731, as described in Claim 1, revolve around a memory module that incorporates a circuit with first and second sets of bi-directional ports, a switching sub-circuit for selective coupling between these ports, and, crucially, a dedicated correction circuit within each of these ports configured to reduce noise in transmitted signals.

Below are selected prior art references from the "Patent citations" section of US10025731 on Google Patents, along with an assessment of their potential to anticipate Claim 1 under 35 U.S.C. § 102:

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1. U.S. Patent No. 6,374,323 B1

• Full Citation: Pettey et al., U.S. Patent No. 6,374,323 B1, "Memory module."
• Publication/Filing Date: Filed May 22, 1998; Granted April 16, 2002.
• Brief Description: This patent describes a fundamental memory module comprising a printed circuit board, a connector, and a plurality of memory integrated circuit devices. It details the physical arrangement and interconnection of these components, focusing on the electrical pathways for data and control signals.
• Potential Anticipation of Claim(s) under 35 U.S.C. § 102: While US6374323B1 establishes the basic structure of a memory module, including a PCB, connector, and memory devices, it does not disclose the active "circuit" elements central to US10025731's Claim 1. Specifically, it lacks a switching sub-circuit for selective port coupling and, more importantly, individual noise correction circuits within each port. Therefore, it does not anticipate the key functional aspects of Claim 1 related to load isolation and active noise reduction.

2. U.S. Patent No. 6,857,038 B1

• Full Citation: Johnson et al., U.S. Patent No. 6,857,038 B1, "Modular buffer for memory modules with improved buffering."
• Publication/Filing Date: Filed September 27, 2001; Granted February 15, 2005.
• Brief Description: This patent introduces a modular buffer designed to be integrated with memory modules. The buffer includes host data pins for connection to a memory controller and memory data pins for connection to memory devices. Its primary purpose is to reduce electrical loading on the memory bus and enhance overall signal integrity through buffering.
• Potential Anticipation of Claim(s) under 35 U.S.C. § 102: This patent is more relevant as it discusses a "modular buffer" acting as a "circuit" with input/output pins (analogous to first and second sets of ports) and aims to improve signal integrity and reduce loading. While the concept of buffering inherently helps with signal quality, US6857038B1 does not explicitly teach a "switching sub-circuit configured to selectively operatively couple one or more ports" or a "correction circuit configured to reduce noise" specifically within each port of the sets of ports, as required by Claim 1 of US10025731. The buffering described is a general improvement rather than specific per-port noise correction.

3. U.S. Patent No. 7,188,198 B2

• Full Citation: Kirkwood et al., U.S. Patent No. 7,188,198 B2, "Fully buffered DIMM with improved read data path."
• Publication/Filing Date: Filed August 31, 2004; Granted March 6, 2007.
• Brief Description: This patent describes a Fully Buffered Dual In-line Memory Module (FBDIMM) architecture, which utilizes an Advanced Memory Buffer (AMB) to handle all signal traffic (data, address, command) between a memory controller and DRAM devices. The AMB re-drives signals to mitigate signal degradation and reduce electrical load.
• Potential Anticipation of Claim(s) under 35 U.S.C. § 102: US7188198B2 details an AMB that functions as a "circuit" with ports, effectively re-driving signals to improve signal integrity, which is a form of noise reduction. However, Claim 1 of US10025731 specifically calls for a "switching sub-circuit configured to selectively operatively couple" and distinct "correction circuits" embedded within each individual port for noise reduction. While an FBDIMM's AMB provides significant signal conditioning, the patent does not clearly articulate the granular, per-port noise correction elements or the explicit selective coupling mechanism described in US10025731's Claim 1.

4. U.S. Patent No. 7,281,084 B2

• Full Citation: Bhakta et al., U.S. Patent No. 7,281,084 B2, "Memory controller with memory power management."
• Publication/Filing Date: Filed September 24, 2004; Granted October 9, 2007.
• Brief Description: This patent discloses a memory controller that implements power management techniques for memory devices. It focuses on dynamically controlling power to individual memory ranks or devices, allowing inactive components to be logically isolated and thereby reducing overall power consumption.
• Potential Anticipation of Claim(s) under 35 U.S.C. § 102: This reference is highly relevant to the "load isolation" and "power dissipation" benefits mentioned in US10025731. The dynamic control of power states to effectively isolate inactive memory components aligns with the function of a "switching sub-circuit configured to selectively operatively couple" ports to achieve logical isolation and power reduction. However, US7281084B2 primarily addresses power management and does not explicitly teach or suggest the integration of "correction circuits configured to reduce noise" within each port of the communication pathways, which is a key distinguishing feature of Claim 1 of US10025731.

5. U.S. Patent Application Publication No. 2007/0055836 A1

• Full Citation: Pettey et al., U.S. Patent Application Publication No. 2007/0055836 A1, "Memory module having improved signal integrity."
• Publication/Filing Date: Filed September 1, 2006; Published March 8, 2007.
• Brief Description: This application describes a memory module that includes a buffer device designed to enhance signal integrity. The buffer re-drives signals and may incorporate elements for impedance matching or other signal conditioning techniques to counteract signal degradation over transmission lines.
• Potential Anticipation of Claim(s) under 35 U.S.C. § 102: This patent application is among the most relevant due to its explicit focus on "improved signal integrity" on a memory module using a "buffer device." This buffer device functions as a "circuit" with associated I/O (ports). The re-driving and signal conditioning mentioned are direct methods of "reducing noise." If the buffer device's architecture implicitly or explicitly includes noise reduction elements integrated with its I/O ports that function as "correction circuits," it could anticipate the signal integrity aspect of Claim 1. However, the extent of anticipation hinges on whether the application details the "correction circuit" within each port and also a "switching sub-circuit configured to selectively operatively couple" the ports as described in Claim 1 of US10025731. While very close in scope regarding signal integrity, the precise combination and granularity of the elements in Claim 1 of US10025731 may still offer patentable distinction.