Obviousness

Obviousness Analysis of US8307116B2 under 35 U.S.C. § 103

This analysis assesses the obviousness of US patent US8307116B2, "Scalable bus-based on-chip interconnection networks," under 35 U.S.C. § 103, using the explicit prior art disclosed within the patent itself. The analysis considers the perspective of a Person Having Ordinary Skill In The Art (POSITA) at the time of the invention's priority date, June 19, 2009.

Person Having Ordinary Skill In The Art (POSITA)

A POSITA in this field would typically possess a bachelor's or master's degree in electrical engineering, computer engineering, or computer science, coupled with several years of experience in designing or analyzing multi-processor architectures, Systems-on-Chip (SoCs), and on-chip networks (NoCs). This individual would be conversant with various network topologies, routing protocols, latency and bandwidth optimization, scalability challenges, and power efficiency considerations in integrated circuit design. Understanding of network "concentration," point-to-point connections, and shared bus architectures would also be expected.

Scope and Content of the Prior Art

The provided authoritative full patent text for US8307116B2 explicitly references one piece of non-patent literature as prior art:

• Kim et al., "Flattened Butterfly Topology for On-Chip Networks," IEEE Computer Architecture Letters, Vol. 6, Issue 2, pp. 37-40. This reference is described in US8307116B2 as discussing "Another example of a concentrated on-chip network" (Description, column 5, lines 16-19).

It is crucial to note that the provided patent document for US8307116B2 does not contain a comprehensive "References Cited" section listing all patent and non-patent literature considered during its prosecution. Therefore, this obviousness analysis is constrained by the explicitly provided prior art reference and general knowledge within the field as of the priority date.

General knowledge in the field at the time of the invention would include:

• The widespread adoption and growth of multi-core processors and SoCs.
• The known challenges in on-chip interconnection networks regarding scalability, communication latency, and power consumption as the number of processing nodes increased.
• Familiarity with various NoC topologies (ee.g., mesh, torus, butterfly networks) and associated routing algorithms.
• The use of both dedicated point-to-point communication channels and shared communication channels (buses).
• Techniques for reducing the "hop count" (the number of intermediate routing devices a data packet traverses) to minimize latency.
• The concept of network concentration, where multiple processing elements share a single router or network interface to reduce the overall network resources and complexity.

Differences Between the Prior Art and the Claims & Motivation to Combine

The independent claims of US8307116B2 (Claims 1, 8, and 14) describe a multinodal on-chip network with physical communication channels arranged in horizontal and vertical rows, where the number of channel rows equals the number of nodes in that row. Key features include the ability of at least one channel to route data from a first node to two or more destination nodes (multicast/broadcast capability) and the arrangement of channels to route data between any two nodes in a maximum of two hops.

Analysis Based on Kim et al. and General Knowledge:

A POSITA, recognizing the limitations of existing on-chip networks (as articulated in the background of US8307116B2, such as poor scalability and high latency), would be motivated to seek solutions that enhance network efficiency. Kim et al.'s "Flattened Butterfly Topology" would be a highly relevant starting point because it explicitly addresses these challenges by proposing a "concentrated on-chip network."

The motivations for a POSITA to combine or modify the teachings of Kim et al. with general knowledge to arrive at the claimed invention include:

1. Improving Scalability and Efficiency: Both US8307116B2 and Kim et al. share the goal of creating more scalable and efficient on-chip networks for increasing node counts. This common objective would drive a POSITA to integrate known optimization techniques.
2. Utilizing Common On-Chip Layouts: Implementing a multinodal array with communication channels extending along horizontal and vertical rows is a standard architectural approach in NoC design (e.g., mesh, torus). A POSITA would routinely apply such physical layouts to any logical topology, including a concentrated one like the Flattened Butterfly, for ease of fabrication and routing.
3. Optimizing Channel Density: The specific claim of having the number of channel rows equal to the number of nodes in that row (Claim 1) represents an optimization of communication resources. A POSITA would be motivated to design the channel infrastructure to match the number of nodes to ensure adequate bandwidth and connectivity, or to optimize for area and power, which are routine engineering considerations in NoC design. This is a predictable design choice given the need for efficient communication in a concentrated network.
4. Implementing Multicast/Broadcast Functionality: The capability to route data from a single node to two or more other destination nodes via a "single physical communication channel" (Claims 1, 8, 14) implies multicast or shared bus functionality. US8307116B2 itself describes "shared communication channels 405 that may function as a shared busway for routing data from a starting node 104(1) to multiple destination nodes" (Description, column 5, lines 11-14). Multicast and broadcast features are well-known in general networking and desirable in multi-processor environments (e.g., for cache coherence, global synchronization). A POSITA would find it obvious to integrate such functionality into a concentrated on-chip network to improve overall system efficiency, especially where resources are shared.
5. Achieving a Low Hop Count (Maximum Two Hops): The emphasis on routing data between any two nodes using a "maximum of two hops" is a key performance metric. Concentrated networks like the Flattened Butterfly are inherently designed to reduce hop counts compared to simpler topologies. US8307116B2 itself discusses how "Longer point-to-point channels 403 may serve to minimize latency in the network by reducing the number of hops" (Description, column 5, lines 3-6). A POSITA, focused on minimizing latency, would be highly motivated to deploy strategies such as longer direct links or optimized shared buses (as suggested by the patent itself) within a concentrated architecture to achieve such a low hop count, as this is a fundamental design goal in NoC optimization. This represents a predictable engineering effort to enhance a known system feature.

Reasonable Expectation of Success

A POSITA would have a reasonable expectation of success in achieving the claimed features by combining the principles of a concentrated on-chip network (as described by Kim et al.) with general knowledge and common design practices in the field. The architectural components (nodes, channels, routers), routing strategies (multicast, hop reduction), and layout considerations (horizontal/vertical arrays) were all well-understood. The specific quantitative relationship of channels to nodes, and the achievement of a two-hop maximum, would be attainable through routine engineering design, simulation, and optimization, not requiring undue experimentation or yielding unexpected results. The benefits of such a combination, namely improved scalability and reduced latency, would be readily apparent and expected by a POSITA.

Conclusion on Obviousness

Based on the explicit disclosure of "Flattened Butterfly Topology for On-Chip Networks" by Kim et al. as a concentrated on-chip network, combined with the general knowledge possessed by a POSITA regarding NoC design and optimization:

The independent claims (Claims 1, 8, and 14) of US8307116B2 would likely be considered obvious. A POSITA, driven by the persistent challenges in on-chip network scalability and latency, would have been motivated to take a concentrated network architecture (like that of Kim et al.) and apply routine design enhancements. These enhancements would include: using a grid-like physical layout, optimizing channel density by ensuring the number of channel rows matches node rows in each dimension, incorporating multicast/shared bus capabilities for efficient multi-destination routing, and employing strategies such as longer direct links to reduce the maximum hop count to two for any-to-any communication. Such modifications and combinations represent predictable steps of a POSITA aiming to improve the performance, efficiency, and scalability of on-chip interconnection networks.