Obviousness

Obviousness Analysis under 35 U.S.C. § 103 for US Patent 9337193

This analysis identifies combinations of prior art references that would render the claims of US Patent 9337193 obvious to a person having ordinary skill in the art (PHOSITA), and explains the motivation for combining them.

Independent Claim 1 of US9337193

Independent Claim 1 defines a semiconductor device comprising:

1. At least two fin-shaped structures disposed on a substrate.
2. A gate structure covering the fin-shaped structures.
3. At least two epitaxial structures, disposed at one side of the gate structure and respectively directly contacting each fin-shaped structure, wherein the epitaxial structures are spaced apart from each other.
4. At least two caps, respectively surrounding the epitaxial structures, wherein at least two adjacent caps are merged together.

The distinguishing features of Claim 1, particularly in combination, are the presence of spaced-apart epitaxial structures and merged adjacent caps that surround these epitaxial structures. The patent itself identifies a problem of "unwanted lattice defects on their interfaces" between adjacent epitaxial structures [cite: The full patent text, Description of the Prior Art]. The solution proposed is to have few lattice defects and enhanced stresses by using this specific configuration [cite: The full patent text, Summary of the Invention].

Prior Art References for Obviousness

The following prior art references are identified from the "Citations (33)" section of US9337193 as particularly relevant:

• US9006805B2 (Semiconductor device): This is the parent application of US9337193, filed on August 7, 2013, and its disclosure is incorporated by reference in its entirety [cite: The full patent text, CROSS REFERENCE TO RELATED APPLICATIONS]. As such, it is highly likely to disclose most, if not all, of the structural features of US9337193, including fin-shaped structures, gate structures, epitaxial source/drain regions, and possibly individual caps over these regions.
• US20040195624A1 (Strained silicon fin field effect transistor): This reference teaches the fundamental concept of FinFETs and the use of strained silicon for performance enhancement, which often involves epitaxial growth in source/drain regions.
• US20110298058A1 (Faceted epi shape and half-wrap around silicide in s/d merged finfet): The title of this reference explicitly mentions "s/d merged finfet" and "half-wrap around silicide," suggesting the concept of merging elements in the source/drain regions and using capping layers for silicide formation.

Obviousness Combination and Motivation

A person having ordinary skill in the art (PHOSITA) would have been motivated to combine the teachings of these references to achieve the claimed invention, particularly in light of known challenges in semiconductor device fabrication.

Combination: US9006805B2 in view of US20110298058A1 and general PHOSITA knowledge.

1. US9006805B2 (Primary Reference): As the parent application, US9006805B2 would teach the foundational elements of a FinFET device, including:

   • (a) At least two fin-shaped structures disposed on a substrate.
   • (b) A gate structure covering the fin-shaped structures.
   • (c) At least two epitaxial structures, disposed at one side of the gate structure and respectively directly contacting each fin-shaped structure. US9006805B2 would teach the formation of epitaxial source/drain regions for FinFETs, a common technique for introducing strain and enhancing performance, as also generally taught by US20040195624A1. US9006805B2 would likely show these epitaxial structures as distinct and potentially spaced apart to maintain individual fin integrity and crystalline quality. Furthermore, individual caps over these epitaxial structures would be a known technique for facilitating subsequent processing steps like silicide formation.

2. Motivation from PHOSITA Knowledge and US20110298058A1:

   • Problem Recognition: A PHOSITA, as explicitly noted in the background of US9337193, would be aware that "two adjacent epitaxial structures within the semiconductor device often generate unwanted lattice defects on their interfaces" when they are closely spaced or directly merged [cite: The full patent text, Description of the Prior Art]. This problem significantly impacts device performance.
   • Desire for Merged S/D: US20110298058A1 teaches the concept of "s/d merged finfet," which implies a desire for a larger or continuous source/drain region, likely to reduce resistance or improve contact area.
   • Combining Solution: A PHOSITA, seeking to achieve the benefits of a "merged S/D" configuration (as suggested by US20110298058A1) while simultaneously mitigating the known problem of lattice defects between directly merged epitaxial structures, would be motivated to:
     • Maintain the epitaxial structures spaced apart from each other (as likely shown or implied by US9006805B2) to preserve their crystalline quality and avoid interface defects.
     • Then, grow a subsequent capping layer (such as monocrystalline silicon, as described in US9337193 [cite: The full patent text, Detailed Description, FIG. 7]) over these spaced-apart epitaxial structures, allowing this capping layer to merge together between the adjacent epitaxial structures. This merged cap would provide the desired contiguous surface for subsequent contact formation (e.g., silicide, as implied by "half-wrap around silicide" in US20110298058A1), effectively creating a "merged S/D" contact region without compromising the quality of the underlying strained epitaxial structures.

This combination of maintaining spaced epitaxial structures to avoid defects, while merging a subsequent cap layer to create a larger, continuous contact region, represents an obvious design choice for a PHOSITA trying to optimize FinFET performance and address known manufacturing challenges. The structure and method disclosed in US9337193, where "the silicon cap 68 continuously grows on the surface of each of epitaxial structure 66 and gradually fills up the space between two adjacent epitaxial structures 66 until two adjacent silicon caps 68 merge together" [cite: The full patent text, Detailed Description, FIG. 7], directly implements this obvious solution.

Therefore, the combination of US9006805B2 (for the basic FinFET with epitaxial S/D and individual caps) with the motivation from US20110298058A1 (for merged S/D) and the general understanding of epitaxial defect challenges would render Claim 1 of US9337193 obvious.