Obviousness

Under 35 U.S.C. § 103, a patent claim is considered obvious if the differences between the claimed invention and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art (POSITA). This analysis requires identifying: 1) the scope and content of the prior art, 2) the differences between the prior art and the claims at issue, 3) the level of ordinary skill in the pertinent art, and 4) any objective indicia of non-obviousness (e.g., commercial success, long-felt need, failure of others).

For the purpose of this analysis, we will strictly use the prior art references explicitly cited within US patent 9299730B2 in the "Citations" section and the problem statement outlined in its "Background" section. The priority date for US9299730B2 is September 19, 2012. All cited references in the "Citations" section predate this.

Independent Claims for Analysis:

• Claim 1 (TFT array substrate): A TFT array substrate comprising a substrate, a first insulation layer, a capacitor (with a lower electrode on the first insulation layer, and an upper electrode arranged to overlap with the whole lower electrode, extending beyond an edge of the lower electrode, and having an opening, wherein the upper electrode is insulated from the lower electrode by a second insulation layer), an inter-layer insulation film covering the capacitor, a node contact hole (in the inter-layer insulation film and the second insulation layer, and within the opening), and a connection node on the inter-layer insulation film electrically coupling the lower electrode and at least one TFT through the node contact hole.
• Claim 10 (OLED display): An OLED display comprising similar structural elements to Claim 1, but specifically within the context of an OLED display with a scan line, data line, driving voltage line, pixel circuit (including at least one TFT and the capacitor), and an OLED.

Prior Art References (from US9299730B2 "Citations"):
Among the listed prior art, several patents disclose OLED displays and manufacturing methods, which are highly relevant to US9299730B2:

• US20120146004A1: "Organic Light-Emitting Display Apparatus and Method of Manufacturing the Same" (Priority Date: 2010-12-14)
• US20130063330A1: "Organic Light-Emitting Display Device" (Priority Date: 2011-09-08)
• KR20080085411A: "OLED display panel and method of manufacturing same" (Priority Date: 2007-03-20)

The Known Problem and Motivation for Combination:
The background section of US9299730B2 explicitly states a known problem in the prior art: "In a system in which a great number of large-sized panels are manufactured at the same time, a misalignment may occur between a substrate and a mask or a light exposure device within a tolerance (or tolerance level) of process equipment during a patterning process." It further clarifies the consequence: "Contrary to an intention of the design, an overlay deviation may occur between both of the electrodes of the capacitor due to the misalignment. Due to the overlay deviation, a capacitance may be generated that is different from a designed value, thereby resulting in low-gradation spots, abnormal colors, or the like."

Therefore, a POSITA in the field of display manufacturing would have been clearly motivated to address the problem of capacitance variation caused by manufacturing overlay deviations to improve display quality and reliability. The stated objective of US9299730B2 is to provide "a storage capacitor structure for maintaining a capacitance to be substantially constant even though an overlay deviation occurs."

Combination of Prior Art for Obviousness:

Primary Reference:
Let's consider US20120146004A1 ("Organic Light-Emitting Display Apparatus and Method of Manufacturing the Same") as a primary reference. Given its title and assignee (Samsung Mobile Display Co., Ltd., which is related to the current assignee Samsung Display Co Ltd), it is highly likely to disclose a conventional OLED display (or TFT array substrate) including:

• A substrate.
• Various insulation layers (e.g., first insulation layer, second insulation layer, inter-layer insulation film).
• A pixel circuit with at least one TFT.
• A storage capacitor comprising a lower electrode and an upper electrode, separated by a dielectric (e.g., a second insulation layer).
• Standard lines such as scan lines, data lines, and driving voltage lines, as well as an OLED.
• Means for electrically coupling the capacitor electrodes to the TFTs in the pixel circuit through contact holes.

Missing Elements from a Conventional Reference:
While US20120146004A1 (or similar references) would disclose the general components, it is unlikely to specifically teach the precise capacitor geometry claimed in US9299730B2, particularly:

1. An upper electrode "arranged to overlap with the whole lower electrode".
2. The upper electrode "extending beyond an edge of the lower electrode".
3. The upper electrode "having an opening".
4. A node contact hole "within the opening" of the upper electrode, connecting to the lower electrode.

Motivation and Means to Combine/Modify:

A POSITA, motivated by the known problem of capacitance variation due to overlay deviation (as described in the Background of US9299730B2), would seek to design a storage capacitor that maintains a stable capacitance regardless of typical manufacturing misalignments.

1. Ensuring Stable Overlap Area: To ensure the effective overlapping area ('A' in the capacitance formula C = εA/d) remains constant even with shifts between the two electrodes, it is a well-established engineering principle in layered structures (such as capacitors in integrated circuits) to make one electrode sufficiently larger than the other so that the smaller electrode is always fully contained within the larger one, within expected process tolerances. Therefore, a POSITA would find it obvious to modify the capacitor structure of US20120146004A1 such that the upper electrode is designed to be larger than, and completely encompass, the lower electrode. This directly leads to an "upper electrode arranged to overlap with the whole lower electrode" and "extending beyond an edge of the lower electrode." The patent itself highlights that "the area of the upper electrode 1142 may be as large as that of the lower electrode 1141 so that the capacitance may be maintained (e.g., always maintained) to be substantially constant even though a shift occurs."

2. Forming a Connection Node through an Opening: If the upper electrode is designed to completely cover the lower electrode for optimal capacitance stability, an electrical connection to the lower electrode would still be required for the pixel circuit. In multi-layered semiconductor device fabrication, creating an opening (e.g., a via or hole) in an overlying conductive or insulating layer to expose a portion of an underlying layer for electrical contact is a routine design practice. Thus, a POSITA would find it obvious to form an "opening" in the upper electrode to expose a part of the lower electrode, and then form a "node contact hole" "within this opening" through subsequent insulation layers to establish the necessary electrical connection to the lower electrode. This allows the lower electrode to be fully overlapped by the upper electrode while still being connectable. The patent provides an example of this opening being a "simple closed curve" or "doughnut shape", which are specific implementations of a general opening.

Conclusion:
Claims 1 and 10 of US9299730B2 would be rendered obvious by combining the teachings of US20120146004A1 (or another similar OLED display/TFT array substrate patent from the "Citations" list disclosing a basic pixel circuit with a storage capacitor) with the general knowledge in the art regarding mitigating manufacturing misalignment in layered structures and forming electrical contacts through layers. The motivation to combine these elements is clearly established by the widely known problem of capacitance variation due to overlay deviation in display manufacturing, as acknowledged in the background of US9299730B2 itself. A POSITA would have been driven to implement these straightforward design choices to achieve a stable capacitance, leading directly to the claimed capacitor structure and its integration into a TFT array substrate and OLED display.