Obviousness

To analyze the obviousness of US patent 92813314 under 35 U.S.C. § 103, we must identify differences between the claimed invention and the prior art, and determine if a person having ordinary skill in the art (POSA) would have been motivated to combine prior art elements to achieve the claimed invention. The analysis relies solely on the prior art explicitly referenced or described as known within the provided patent text.

1. Scope and Content of the Prior Art

The patent text describes or references the following as known prior art:

• Non-volatile memory technologies: EEPROM and flash memory, including NAND structures with series-connected floating-gate transistors (memory cells) and select gate transistors (FIGS. 1, 2A, 2B, 3).
• Charge storage mechanisms:
  • Conductive floating gates (e.g., polysilicon) (FIG. 5A).
  • Dielectric charge trapping regions, particularly ONO (Oxide-Nitride-Oxide) structures, where a triple layer of silicon oxide, silicon nitride, and silicon oxide is sandwiched between a control gate and a substrate. These cells are programmed by injecting electrons into the nitride. [cite: "Chan et al., “A True Single-Transistor Oxide-Nitride-Oxide EEPROM Device,” IEEE Electron Device Letters, Vol. EDL-8, No. 3, March 1987, pp. 93-95.", "Nozaki et al., “A 1-Mb EEPROM with MONOS Memory Cell for Semiconductor Disk Application,” IEEE Journal of Solid-State Circuits, Vol. 26, No. 4, April 1991, pp. 497-501."].
  • TANOS structures (TaN—Al2O3—SiN—SiO2) also use charge trapping in a nitride layer.
• Electrical isolation techniques:
  • Shallow Trench Isolation (STI) structures, typically formed from silicon oxide or TEOS, to provide electrical isolation between adjacent NAND strings (FIG. 2B).
  • "Bit line air gaps" for electrical isolation between adjacent NAND strings (FIG. 2B).
• Semiconductor Fabrication Processes:
  • Deposition techniques: Chemical Vapor Deposition (CVD), metal organic CVD, Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), Low Pressure CVD (LPCVD), Plasma-Enhanced CVD (PECVD), and flowable CVD films (e.g., depositing silicon, nitrogen, and hydrogen for sacrificial material). [cite: "The tunnel oxide layer 820 is a thin layer of oxide (e.g., SiO 2 ) grown in one embodiment, although different materials and processes can be used. Chemical vapor deposition (CVD) processes, metal organic CVD processes, physical vapor deposition (PVD) processes, atomic layer deposition (ALD) processes, thermal oxidation or other suitable techniques can be used.", "In one embodiment, the silicon nitride is formed using low pressure chemical vapor deposition (LPCVD) technology.", "In one embodiment, the silicon nitride is formed using plasma-enhanced chemical vapor deposition (PECVD) technology.", "In one embodiment, the sacrificial materials is a flowable CVD film. This film can be formed using a high-density plasma CVD system, a plasma enhanced CVD system, and/or a sub-atmospheric CVD system, among other systems."].
  • Etching techniques: General etching to form lines and structures, including selective etching (FIG. 8B, 8C, 10E).
  • Oxidation techniques: High-temperature oxidation (e.g., over 1000° C with ambient oxygen gas) or low-temperature oxidation (e.g., 400° C in high-density Krypton plasma) for forming silicon oxide. [cite: "For sidewall oxidation, the device may be placed in a furnace at a high temperature (e.g., over 1000 degrees Celsius) and with some fractional percentage of ambient oxygen gas, so that the exposed surfaces oxidize.", "An alternative to high temperature oxide growth is low temperature (e.g., 400 degrees Celsius) oxide growth in high density Krypton plasma."].
  • Doping: Implanting suitable dopants for source/drain regions.
  • Patterning techniques: Spacer-assisted patterning, nano-imprint patterning. [cite: "Spacer-assisted patterning, nano-imprint patterning, and other patterning techniques can also be used to form strips at reduced feature sizes."].

2. Differences Between the Claimed Invention and the Prior Art

The key distinguishing features of US9281314, as highlighted in its abstract and independent claims, are:

• Selective placement of silicon nitride: Silicon nitride covers the silicon oxide adjacent to the word lines (for protection), but does not cover the silicon oxide adjacent to the charge storage regions of the memory cells.
• Use of a sacrificial material: A sacrificial material is formed and then etched back to precisely control the formation and location of the silicon nitride layer, specifically ensuring it is below word lines but above charge storage regions during nitride deposition.
• Air gaps for electrical isolation: Word line air gaps are formed between neighboring lines of memory cell stacks, and these air gaps are adjacent to the portions of silicon oxide that are next to the charge storage regions.

3. Level of Ordinary Skill in the Pertinent Art

A person having ordinary skill in the art (POSA) in this field would possess expertise in semiconductor device fabrication, particularly for non-volatile memory such as NAND flash, and a good understanding of material properties (e.g., dielectrics like silicon oxide and silicon nitride) and their electrical characteristics. They would be familiar with common deposition, etching, and patterning techniques used in microfabrication.

4. Obviousness Analysis (Combination of Prior Art)

The patent explicitly identifies a problem with existing techniques: "some conventional techniques for combating breakdown voltage lead to other problems, such as undesirably trapping charges in dielectric materials. These trapped charges can impair device performance." [cite: "With ever decreasing size of features, combating breakdown voltage can be difficult. One type of voltage breakdown occurs between neighboring word lines. As the distance between word lines decreases, breakdown voltage may become a greater problem. Moreover, some conventional techniques for combating breakdown voltage lead to other problems, such as undesirably trapping charges in dielectric materials. These trapped charges can impair device performance."]. Specifically, FIG. 6 and its accompanying description illustrate a scenario where silicon nitride covering sidewalls adjacent to charge storage regions leads to trapped charges, altering the neutral threshold voltage (VTH) and degrading cell current.

Given this context, a POSA would be motivated to combine known elements and techniques to overcome these problems.

Motivation to Combine:
The explicit problem identified by the patent – that silicon nitride can trap charges which degrade memory cell operation if located near the charge storage region (as depicted in FIG. 6) – would strongly motivate a POSA to avoid placing silicon nitride in that specific area. Concurrently, the need for increased breakdown voltage between word lines due to decreasing feature sizes would motivate the use of superior insulators.

Combination Argument:

1. Awareness of Charge Trapping: A POSA, having knowledge of ONO-type memory cells (e.g., as described by Chan et al. [cite: "Such a cell is described in an article by Chan et al., “A True Single-Transistor Oxide-Nitride-Oxide EEPROM Device,” IEEE Electron Device Letters, Vol. EDL-8, No. 3, March 1987, pp. 93-95."], Nozaki et al. [cite: "See also Nozaki et al., “A 1-Mb EEPROM with MONOS Memory Cell for Semiconductor Disk Application,” IEEE Journal of Solid-State Circuits, Vol. 26, No. 4, April 1991, pp. 497-501,"], and TANOS structures), would be acutely aware that silicon nitride is a charge-trapping material. Therefore, if the patent explicitly points out (as in FIG. 6) that placing nitride adjacent to unintended charge storage regions (i.e., the memory cell's charge storage region) leads to detrimental charge trapping and degraded performance, a POSA would naturally seek to eliminate nitride from that problematic location.

2. Motivation for Selective Placement: To address the dual needs of protecting word lines (where nitride is beneficial and less problematic for charge trapping since word lines are connected to peripheral circuitry that can compensate for trapped charges [cite: "However, the word line 528 can be connected to peripheral circuitry such as word line drivers, etc. In other words, the word line 528 is not floating or otherwise surrounded by insulation. Thus, positive charges can be provided (or negative charges removed) by the peripheral circuitry to balance out any negative charges in the silicon nitride region 534 that is adjacent to the word line 528 ."]) and avoiding charge trapping near memory cell charge storage regions, a POSA would be motivated to implement selective deposition of silicon nitride.

3. Achieving Selective Deposition with Sacrificial Layers and Etch-back: The use of sacrificial layers in semiconductor manufacturing, followed by etch-back processes, is a well-established technique for creating intricate patterns, spacers, and selectively exposing or covering specific regions. The patent itself describes flowable CVD films (e.g., depositing silicon, nitrogen, and hydrogen) for sacrificial material and etching back to a precise level (below word lines but above charge storage regions). [cite: "One embodiment includes a method that uses a sacrificial material to control formation of a silicon nitride layer when forming a memory device. Lines of memory cell stacks are formed. Each stack has a word line and associated memory cells. Silicon oxide is formed on sidewalls of the lines of the memory cell stacks. A sacrificial material is formed between the lines of the memory cell stacks after forming the silicon oxide. The top of the sacrificial material is below the word lines but above charge storage regions of the memory cells. Thus, a portion of the silicon oxide remains exposed after forming the sacrificial material. Silicon nitride is formed on the sidewalls of the exposed silicon oxide. The sacrificial material is removed while leaving the silicon oxide on the sidewalls of the lines of memory cell stacks and the silicon nitride on the sidewalls of the silicon oxide adjacent to the word lines."]. A POSA would routinely employ such known techniques to achieve the desired selective placement of silicon nitride.

4. Incorporating Air Gaps for Isolation: The patent mentions "bit line air gaps" as an existing form of electrical isolation between NAND strings [cite: "In one embodiment, electrical isolation between adjacent NAND strings 300 is provided by the use of air gaps. These may be referred to a “bit line air gaps” due to their orientation relative to the direction of the bit lines (which may extend in the same direction as the NAND strings 300 ."]. Air is known to be an excellent insulator. Faced with the problem of decreasing feature sizes leading to breakdown voltage issues between word lines [cite: "With ever decreasing size of features, combating breakdown voltage can be difficult. One type of voltage breakdown occurs between neighboring word lines. As the distance between word lines decreases, breakdown voltage may become a greater problem."], a POSA would be motivated to use air gaps for superior electrical isolation between word lines, especially in the regions where problematic charge-trapping silicon nitride has been intentionally excluded. The space left by the removed sacrificial material naturally lends itself to forming air gaps. [cite: "Also, the air gap can be formed in the space vacated by the sacrificial material. The air gap provides for good electrical isolation and high voltage breakdown between the word lines."].

Conclusion:

The core invention of US9281314 is the selective placement of silicon nitride and the use of air gaps, enabled by a sacrificial layer and etch-back process. The patent itself clearly articulates the problem solved (undesirable charge trapping in nitride near charge storage regions and breakdown voltage issues between word lines) and points to the known characteristics of silicon nitride (charge trapping) and air gaps (good electrical isolation). A POSA, armed with knowledge of existing NAND flash memory fabrication, the charge-trapping nature of silicon nitride from ONO device prior art (Chan et al., Nozaki et al.), the benefits of air gaps for electrical isolation, and standard semiconductor processing techniques like sacrificial layers and selective etching, would have been motivated to combine these known elements. The motivation would be to mitigate the described charge trapping issue near charge storage regions while simultaneously providing word line protection and improved inter-word line isolation, all of which are explicitly stated problems and solutions within the field. Therefore, the claimed invention, which essentially combines known materials with known fabrication methods to solve an identified problem, would likely be considered obvious to a POSA.