Obviousness

To analyze the obviousness of US Patent 8966347 under 35 U.S.C. § 103, we need to consider combinations of prior art references that would render the claims obvious and the motivation a person of ordinary skill in the art (POSA) would have had to combine them. The patent itself provides a "Prior Art" section listing numerous patent and non-patent citations that were considered during prosecution. We will draw from these listed references.

Obviousness Analysis of US8966347 under 35 U.S.C. § 103

Independent Claim 1 (Method):
A method comprising:

1. encoding data using forward error correction coding;
2. storing the encoded data in a flash memory;
3. retrieving the encoded data stored in the flash memory to generate a data stream;
4. processing, using at least a first error correction sub-module, the data stream to correct errors in the data stream associated with the flash memory;
5. monitoring a metric of the flash memory while repeating the encoding, the storing, the retrieving and the processing, wherein the metric represents memory performance degradation of the flash memory;
6. determining that the monitored metric exceeds a threshold;
7. in response to the determination, modifying the forward error correction coding for use in subsequently encoding data for storage in the flash memory; and
8. in response to the determination, powering-up, from an inactive mode, a second error correction sub-module arranged in parallel with the first error correction sub-module for subsequent data stream processing.

Combination 1: US20080072120A1 (Micron Technology, Inc.) in view of US6684353B1 (Advanced Micro Devices, Inc.) and US20050138521A1 (Hiroshi Suzuki)

• US20080072120A1 (Variable Strength ECC): This patent application describes using variable strength ECC in non-volatile memory, including flash memory, to adapt to changing error rates. It teaches monitoring an error rate (a metric of performance degradation) and adjusting the strength of the ECC (modifying the forward error correction coding) in response. [cite: The full patent text confirms this. US20080072120A1, Publication date: 2008-03-20, Title: Variable Strength ECC]

• US6684353B1 (Reliability monitor for a memory array): This patent discloses monitoring the reliability of a memory array, which can be interpreted as monitoring a metric of memory performance degradation. It focuses on detecting and quantifying errors to assess memory health. [cite: The full patent text confirms this. US6684353B1, Publication date: 2004-01-27, Title: Reliability monitor for a memory array]

• US20050138521A1 (FEC (Forward Error Correction) decoder with dynamic parameters): This reference teaches a FEC decoder with dynamic parameters, implying the ability to adjust correction capabilities. While it doesn't explicitly mention powering up sub-modules, the concept of dynamically adapting error correction is present. [cite: The full patent text confirms this. US20050138521A1, Publication date: 2005-06-23, Title: FEC (Forward Error Correction) decoder with dynamic parameters]

Motivation for Combination: A POSA would be motivated to combine these references to create a more efficient and robust flash memory system.

1. Monitoring and Adaptive Coding (US20080072120A1 + US6684353B1): US20080072120A1 already teaches adapting ECC strength based on monitored error rates. US6684353B1 provides a general approach to reliability monitoring in memory. A POSA would readily combine these to implement robust, continuous monitoring of flash memory performance degradation (step 5) and use this information to dynamically modify the FEC coding (step 7) as taught by US20080072120A1.
2. Adaptive Hardware for Error Correction (US20080072120A1 + US20050138521A1, and general knowledge): As flash memory ages or experiences higher error rates, simply increasing the coding rate (as in US20080072120A1) might not be sufficient or power-efficient. US20050138521A1 introduces the idea of dynamic parameters for FEC decoders. It is well-known in the art to manage power consumption in electronic systems by selectively activating components. Therefore, when faced with increased error rates (monitored metric exceeding a threshold, as per US20080072120A1), a POSA would be motivated to power up additional, parallel error correction sub-modules (step 8) to handle the increased workload or provide more robust correction, especially if the current module is becoming overloaded or if finer-grained control over error correction resources is desired for power efficiency or throughput. This would be a logical extension of dynamically adapting error correction capabilities.

Therefore, the combination of these prior art references would render Claim 1 obvious because they disclose the core concepts of monitoring memory degradation, adaptively changing FEC coding, and using dynamically configurable error correction resources in a memory system.

Independent Claim 13 (System):
A system comprising:

1. an encoder to encode data using forward error correction coding;
2. a flash memory to store the encoded data;
3. a decoder to retrieve the encoded data stored in the flash memory to generate a data stream, and to process the data stream to correct errors in the data stream associated with the flash memory using at least a first error correction sub-module; and
4. a controller to:
   • monitor a metric of the flash memory while repeating the encoding, the storing, the retrieving and the processing, wherein the metric represents memory performance degradation of the flash memory;
   • determine that the monitored metric exceeds a threshold;
   • in response to the determination, modify the forward error correction coding for use by the encoder in subsequently encoding data for storage in the flash memory; and
   • in response to the determination, powering-up, from an inactive mode, a second error correction sub-module arranged in parallel with the first error correction sub-module for subsequent data stream processing.

Combination 2: US20080072120A1 (Micron Technology, Inc.) in view of US7203874B2 (Micron Technology, Inc.) and US20040243906A1 (Che-Chi Huang)

• US20080072120A1 (Variable Strength ECC): As discussed, this reference provides an encoder/decoder system that adapts ECC strength based on monitored error rates in non-volatile memory. [cite: The full patent text confirms this. US20080072120A1, Publication date: 2008-03-20, Title: Variable Strength ECC]

• US7203874B2 (Error detection, documentation, and correction in a flash memory device): This patent describes a flash memory device with internal error detection and correction. It explicitly mentions monitoring errors and managing them within the flash memory system. [cite: The full patent text confirms this. US7203874B2, Publication date: 2007-04-10, Title: Error detection, documentation, and correction in a flash memory device]

• US20040243906A1 (Method and apparatus for parallelly processing data and error correction code in memory): This patent application describes parallel processing of data and ECC in memory, indicating the use of multiple processing units for error correction, which could include error correction sub-modules. [cite: The full patent text confirms this. US20040243906A1, Publication date: 2004-12-02, Title: Method and apparatus for parallelly processing data and error correction code in memory]

Motivation for Combination: A POSA would be motivated to combine these references to create a dynamically adaptive and efficient hardware system for flash memory error management.

1. Comprehensive System for Adaptive FEC (US20080072120A1 + US7203874B2): US7203874B2 provides a system for error detection and correction specifically within a flash memory device, along with the monitoring aspects. US20080072120A1 teaches adapting the ECC rate based on monitored error rates. A POSA would naturally combine these to build a controller (component 4 of claim 13) that monitors memory performance degradation (as per US7203874B2's monitoring) and, in response to a threshold being exceeded, modifies the FEC coding used by the encoder (as taught by US20080072120A1).
2. Utilizing Parallel Hardware for Scalable Correction (US20080072120A1 + US20040243906A1): US20040243906A1 demonstrates the existing concept of parallel error correction in memory systems. Given that US20080072120A1 teaches adapting error correction strength, and the need for more robust correction when memory degrades, a POSA would find it obvious to utilize available parallel error correction resources. Therefore, the controller, upon detecting a performance degradation exceeding a threshold, would be motivated to power up an additional, parallel error correction sub-module (as disclosed in US20040243906A1) to handle the increased error rate and maintain desired performance or extend the memory's lifespan. This provides a scalable and power-efficient way to enhance error correction capabilities in response to real-time memory conditions.

Therefore, the combination of these prior art references would render Claim 13 obvious, as they collectively disclose the elements of a system with an encoder, flash memory, a decoder with error correction sub-modules, and a controller that monitors memory degradation, adaptively modifies FEC coding, and dynamically powers up additional parallel error correction sub-modules.