Patent 8686562
Obviousness
Combinations of prior art that suggest the claimed invention would have been obvious under 35 U.S.C. § 103.
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Obviousness
Combinations of prior art that suggest the claimed invention would have been obvious under 35 U.S.C. § 103.
The search results provide more details on the cited prior art.
1. US6844258B1 (Novellus Systems, Inc.) - "Selective refractory metal and nitride capping"
- This patent is explicitly cited within the US8666562 patent family as relevant to "Selective refractory metal and nitride capping".
- The snippets from the search results (specifically related to US6844258B1) do not directly provide its detailed description in a way that fully addresses its content in relation to the claims of US8686562. However, the title itself is highly suggestive. The phrase "refractory metal and nitride capping" indicates that this patent likely deals with capping layers made of refractory metals and nitrides. Without the full text, it's difficult to ascertain if it describes a refractory metal nitride as the topmost layer of an electrical contact stack for III-V semiconductor devices specifically to prevent contamination of silicon fabrication processes, and the thickness requirement.
- However, other related patents (e.g., US20160190008A1 and US12002679B2, which also cite US6844258B1) discuss tungsten deposition, tungsten-containing materials, titanium nitride (TiN) as under-layers, and fill materials for features like vias and contacts in semiconductor fabrication. US20160190008A1 mentions that examples of under-layers for tungsten include titanium (Ti), titanium nitride (TiN), and tungsten nitride (WN). This confirms that refractory metal nitrides like TiN and WN were known as layers in contact structures.
2. US5514908A (Sgs-Thomson Microelectronics, Inc.) - "Integrated circuit with a titanium nitride contact barrier having oxygen stuffed grain boundaries"
- This patent describes a "titanium nitride contact barrier". While it uses TiN, it's primarily as a barrier layer, often placed underneath the primary metal interconnect to prevent diffusion. The '562 patent specifies the refractory metal nitride as a capping layer forming the top of the electrical contact. The roles are distinct: a barrier layer generally mediates interaction between layers or between a contact and a semiconductor, while a capping layer is typically the outermost layer, often for protection from the environment or subsequent processing steps.
3. US7719030B2 (International Rectifier Corporation) - "Aluminum alloys for low resistance, ohmic contacts to III-nitride or compound semiconductor"
- This patent, from the original assignee of '562, directly addresses "Aluminum alloys for low resistance, ohmic contacts to III-nitride or compound semiconductor". This reference clearly teaches the formation of ohmic contacts to III-nitride (a type of Group III-V) semiconductors using aluminum alloys as part of an electrode stack, which are key components of claims 1 and 13. This fulfills the "plurality of metal layers" (at least including Al) on a "group III-V semiconductor device" (III-nitride). It would represent the "conventional approach" of forming electrode stacks on III-nitride devices prior to the '562 invention.
Obviousness Analysis under 35 U.S.C. § 103
A claim is obvious if "the differences between the claimed invention and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art." This requires identifying:
- The scope and content of the prior art.
- The differences between the prior art and the claims.
- The level of ordinary skill in the pertinent art.
- Secondary considerations (e.g., commercial success, long-felt but unsolved needs, failure of others).
Level of Ordinary Skill in the Art (POSITA): A POSITA in this field would likely have a master's degree in electrical engineering, materials science, or a related field, with several years of experience in semiconductor device fabrication, particularly with compound semiconductors and metallization processes. They would be familiar with different deposition techniques (sputtering, CVD, e-beam), contact formation on III-V devices, and common issues like material diffusion and contamination.
Problem Addressed by US8686562: The '562 patent explicitly states the drawbacks of conventional gold capping layers on III-nitride devices: cost, gold diffusion into the electrode stack and semiconductor, and contamination risk to silicon fabrication processes, making monolithic integration challenging. The invention aims to solve this by providing a contact that reduces contamination risk to silicon process flows, making integration more efficient and cost-effective.
Combination 1: US7719030B2 in view of the Background Art (conventional Ti/Al/Ni/Au stack) and US6844258B1 (or general knowledge of refractory metal nitrides as barrier/capping layers).
- US7719030B2 teaches electrical contacts, including aluminum alloys, for low resistance ohmic contacts to III-nitride semiconductors. This reference directly provides the context of forming contacts on Group III-V semiconductor devices with metal layers (at least including Al). It represents the "plurality of metal layers" aspect of the claims, especially for III-V devices.
- The Background Art of US8686562 explicitly describes the conventional practice of using an "electrical contact stack comprising pure films of titanium, aluminum, and nickel, capped with gold" on III-nitride devices. This confirms the "plurality of metal layers" (e.g., Ti, Al, Ni) and the concept of a "capping layer formed over said plurality of metal layers."
- US6844258B1 (Novellus Systems, Inc.) is titled "Selective refractory metal and nitride capping". While the full text is not provided, the title strongly suggests that refractory metal nitrides were known as capping materials. Furthermore, other related patents (US20160190008A1) explicitly mention TiN and WN as under-layers for tungsten, indicating their use in contact structures. A POSITA would be aware that refractory metal nitrides like TiN are used as diffusion barriers and protective layers in semiconductor manufacturing.
Differences & Motivation to Combine:
The primary difference between the conventional art (as described in the '562 background, including the concepts of US7719030B2) and the claims of '562 is the replacement of the noble metal (e.g., gold) capping layer with a refractory metal nitride capping layer (e.g., TiN or TaN) that consists only of that nitride and forms the top of the electrical contact, and has a greater thickness than the bottommost layer.
A POSITA, confronted with the well-known problems of gold contamination in silicon fabrication processes (explicitly stated in the '562 background as a significant drawback to monolithic integration of III-V and Si devices), would have been motivated to seek alternative capping materials that do not suffer from these drawbacks. Refractory metal nitrides like TiN were known in the art as robust, high-temperature stable, and electrically conductive materials, often used as diffusion barriers or protective coatings in semiconductor devices (e.g., US5514908A teaches TiN as a contact barrier).
The motivation to replace gold with a refractory metal nitride like TiN as the topmost capping layer would be driven by:
- Eliminating Gold Contamination: This is the explicit problem articulated by '562. Replacing gold with a gold-free material would directly address this.
- Cost Reduction: Gold is expensive. Refractory metal nitrides are generally less costly.
- Improved Thermal Stability/Diffusion Prevention: Refractory metal nitrides are known for their high thermal stability and barrier properties, which would prevent unwanted diffusion of underlying metals (or the capping layer itself) into the semiconductor or adjacent device regions during subsequent high-temperature processing or device operation. While US5514908A teaches TiN as a contact barrier, its known properties (stability, barrier function) would suggest its suitability for a capping role if diffusion is a concern.
Considering the knowledge that TiN (a refractory metal nitride) acts as a diffusion barrier (US5514908A) and that gold causes contamination and diffusion issues in conventional III-V contacts (US8686562 Background Art), a POSITA would have found it obvious to replace the problematic gold capping layer with a refractory metal nitride capping layer. The general concept of "refractory metal and nitride capping" (US6844258B1) would further guide this choice.
Regarding the specific limitation that the "capping layer consists only of a refractory metal nitride" and forms the "top of said electrical contact": If the purpose is to prevent contamination from the capping layer and to external process flows, then making it only of the non-contaminating material, and placing it at the top, is a logical design choice. Adding other materials would reintroduce the risk of contamination or negate the benefit.
Regarding the "thickness greater than that of a bottommost layer of said plurality of metal layers": The '562 patent specifies approximate thicknesses: first Ti layer (bottommost) ~100Å, Al layer ~1300Å, second Ti layer ~680Å, and TiN capping layer ~600Å. In this specific embodiment, 600Å is indeed greater than 100Å. This specific thickness ratio, however, appears to be an optimization rather than a fundamental inventive step. Given that capping layers are for protection, making them sufficiently thick for robustness is a matter of routine engineering optimization, especially when replacing a material like gold (which has different physical properties) with a new material like TiN. A POSITA would be motivated to optimize layer thicknesses for performance and reliability, including barrier effectiveness.
Conclusion for Obviousness (Combination 1):
A combination of US7719030B2 (for III-V ohmic contacts and aluminum alloys), the Background Art of US8686562 (for the conventional Ti/Al/Ni/Au stack on III-nitride devices and the problem of gold contamination), and the general knowledge of refractory metal nitrides as barrier/capping layers (informed by US5514908A and the suggestive title of US6844258B1) would have rendered claims 1 and 13 obvious to a POSITA. The motivation would be to overcome the known problems of gold contamination and cost in III-V semiconductor fabrication, by replacing the gold capping layer with a functionally equivalent (or superior, in terms of contamination) refractory metal nitride layer, and optimizing its thickness for protective purposes.
Specifically for Claim 13, which narrows the capping layer to "consisting only of a metal selected from the group consisting of titanium nitride (TiN) and tantalum nitride (TaN)", this would also be obvious. TiN is explicitly taught as a barrier layer in US5514908A. TaN shares similar refractory and barrier properties with TiN, and selecting between known refractory metal nitrides for specific applications based on compatibility and performance is a routine choice for a POSITA. The '562 patent itself lists several refractory metal nitrides (TiN, TaN, ZrN, VN, NbN, MoN, WN2) as possible options.The obviousness of US patent 8686562 under 35 U.S.C. § 103 can be analyzed by considering combinations of prior art references that would have motivated a person having ordinary skill in the art (POSITA) to arrive at the claimed invention. The claimed invention, as defined by independent claims 1 and 13, focuses on an electrical contact for a semiconductor device comprising an electrode stack with metal layers capped by a refractory metal nitride, where this capping layer consists only of the refractory metal nitride, forms the top of the contact, and has a thickness greater than the bottommost metal layer. Claim 13 specifically applies this to Group III-V semiconductor devices, with the capping layer limited to titanium nitride (TiN) or tantalum nitride (TaN).
Level of Ordinary Skill in the Art (POSITA):
A POSITA in this field would typically possess a master's degree in electrical engineering, materials science, or a related discipline, coupled with several years of experience in semiconductor device fabrication, particularly concerning compound semiconductors, metallization processes, and addressing issues like material diffusion and contamination.
Problem Addressed by US8686562:
The patent explicitly identifies significant drawbacks of conventional electrical contacts for III-nitride devices that utilize aluminum in an electrode stack and a gold capping layer. These drawbacks include the high cost of gold, its diffusion into the electrode stack and semiconductor body, and its propensity to contaminate silicon fabrication process flows, thereby hindering the monolithic integration of Group III-V and Group IV semiconductor devices. The disclosed invention aims to overcome these issues by providing a contact that reduces contamination risk to silicon processes, leading to more efficient and cost-effective integration.
Combination of Prior Art for Obviousness:
A compelling argument for obviousness can be made by combining the teachings of US7719030B2, the Background Art described in US8686562, and the general knowledge of refractory metal nitrides as barrier or capping layers (as exemplified by US5514908A and the suggestive title of US6844258B1).
US7719030B2 (International Rectifier Corporation): This patent, from the original assignee of US8686562, teaches "Aluminum alloys for low resistance, ohmic contacts to III-nitride or compound semiconductor". This directly addresses the formation of electrical contacts on Group III-V (III-nitride) semiconductor devices using aluminum-containing metal layers, which aligns with the "plurality of metal layers" aspect of the independent claims. This reference effectively represents the state of the art for forming ohmic contacts on III-V devices.
Background Art of US8686562: The patent's own background section describes the widely used conventional approach: "an electrical contact stack comprising pure films of titanium, aluminum, and nickel, capped with gold" on III-nitride devices. This explicitly discloses the "plurality of metal layers" (e.g., Ti, Al, Ni) and a "capping layer formed over said plurality of metal layers," forming a conventional electrode stack. Crucially, it also highlights the critical problem of gold contamination and diffusion in integrated III-V/Group IV manufacturing.
General Knowledge of Refractory Metal Nitrides as Barrier/Capping Layers (e.g., US5514908A and US6844258B1):
- US5514908A (Sgs-Thomson Microelectronics, Inc.) describes an "Integrated circuit with a titanium nitride contact barrier". This demonstrates that TiN, a refractory metal nitride, was known in the art for its barrier properties within semiconductor contact structures, typically to prevent diffusion.
- US6844258B1 (Novellus Systems, Inc.) is titled "Selective refractory metal and nitride capping". While the full text is not provided, the title strongly indicates that the use of refractory metals and nitrides as capping layers was known. Furthermore, other related patents (e.g., US20160190008A1) refer to titanium (Ti), titanium nitride (TiN), and tungsten nitride (WN) as under-layers for tungsten, confirming the awareness and use of refractory metal nitrides in various roles within contact structures.
Motivation to Combine and Obviousness:
A POSITA, armed with the knowledge from US7719030B2 regarding ohmic contacts to III-nitride devices, and acutely aware of the explicit problems detailed in the background of US8686562 regarding gold capping layers (cost, diffusion, and silicon process contamination), would have been strongly motivated to seek an alternative capping material. Refractory metal nitrides, such as TiN, were well-known in the semiconductor industry for their high thermal stability, electrical conductivity, and diffusion barrier properties (as shown by US5514908A).
The motivation to replace the problematic gold capping layer with a refractory metal nitride like TiN or TaN would stem from:
- Solving the Gold Contamination Problem: This is the most direct and explicitly stated problem that the invention seeks to overcome. Replacing gold with a gold-free, non-contaminating material is a logical solution.
- Reducing Cost: Refractory metal nitrides are generally less expensive than noble metals like gold.
- Leveraging Known Properties: The robust barrier properties and thermal stability of refractory metal nitrides would make them a natural choice for a protective capping layer, especially when diffusion is a concern. The general concept of "refractory metal and nitride capping" from US6844258B1 further supports this direction.
The features of the claims specifying that the "capping layer consists only of a refractory metal nitride" and "forms a top of said electrical contact" would also be an obvious design choice. To effectively prevent contamination from the capping layer itself and to external process flows, making it purely of the desired non-contaminating material and placing it as the outermost layer is a straightforward engineering decision.
Regarding the specific thickness requirement ("thickness greater than that of a bottommost layer of said plurality of metal layers"), the patent describes a first Ti layer (bottommost) of ~100Å and a TiN capping layer of ~600Å in one embodiment. While a specific ratio, ensuring a sufficient thickness for a protective capping layer to be effective, especially when replacing a material with different physical properties (gold vs. TiN), falls within the realm of routine optimization for a POSITA.
Conclusion for Obviousness:
Therefore, the combination of US7719030B2, the explicit problems identified in the Background Art of US8686562 (i.e., gold contamination and cost in III-V device fabrication), and the known use and properties of refractory metal nitrides as barrier or capping layers (as taught by US5514908A and the general knowledge reflected in US6844258B1), would have rendered claims 1 and 13 of US8686562 obvious to a person having ordinary skill in the art at the time of the invention. The motivation for such a combination would be to solve the well-recognized issues associated with gold-capped electrical contacts, particularly in the context of integrating III-V and silicon semiconductor devices.
Generated 7/1/2026, 6:46:22 AM