Prior art

US Patent 8276048, titled "Resource sharing in a telecommunications environment," was granted on September 25, 2012, from an application filed on October 11, 2010, with a priority date of October 12, 2004. This patent describes systems and methods for allocating shared memory and processing resources within a transceiver, particularly for interleavers, deinterleavers, coders, and decoders, based on application requirements like data rate, latency, and bit error rate. The sharing can occur between different latency paths and can be dynamically updated. The patent emphasizes the transmission of information between transceivers regarding their shared memory capabilities during initialization or during active data transmission (SHOWTIME).

To identify the most relevant prior art, I will examine the "Cited By" and "Citations" sections of US8276048B2 as provided in the patent text.

Most Relevant Prior Art for US8276048B2:

The patent explicitly mentions U.S. Pat. Nos. 6,775,320 and 6,778,596 in its background section as describing DSL systems supporting multiple applications and framer/coder/interleaver (FCI) blocks, also referred to as latency paths. These are highly relevant as they establish the context and existing challenges that US8276048B2 aims to address with its resource-sharing approach.

Below are details of the prior art cited in US8276048B2, along with a brief description and potential anticipation under 35 U.S.C. § 102.

1. US6775320B1

• Full Citation: US6775320B1, "Method and a multi-carrier transceiver supporting dynamic switching between active application sets"
• Publication/Filing Date: Priority Date: 1999-03-12, Publication Date: 2004-08-10
• Brief Description: This patent describes a multi-carrier transceiver that supports dynamic switching between active application sets, where different applications can use different latency paths to satisfy their requirements. This directly sets the stage for the problem of managing resources across multiple latency paths for varied applications.
• Potential Anticipated Claim(s): This patent potentially anticipates aspects of claims 1 and 5 relating to a transceiver supporting multiple applications and latency paths with differing requirements, and the idea of configuring these paths based on application needs. Specifically, the concept of a transceiver supporting multiple latency paths for different application requirements, as mentioned in the background of US8276048B2, is directly addressed here.

2. US6778596B1

• Full Citation: US6778596B1 (Note: The provided patent text references "6,778,596" in the background, but the full citation is not immediately available. Assuming the patent is "US6778596B1" based on common patent numbering conventions), "Symbol synchronous device and frequency hopping receiver"
• Publication/Filing Date: Priority Date: 1998-10-09, Publication Date: 2004-08-17
• Brief Description: While the title "Symbol synchronous device and frequency hopping receiver" does not immediately suggest direct relevance to resource sharing in the same way as US6775320B1, its citation in the background of US8276048B2 alongside US6775320B1 implies it also describes aspects of DSL systems supporting multiple applications and FCI blocks. Without the full text of US6778596B1, it's difficult to ascertain its precise contribution to the problem statement. However, its inclusion by the applicant suggests it is relevant to the general architecture or operation of DSL systems with multiple latency paths.
• Potential Anticipated Claim(s): Without the full text, it is difficult to specify exact claims. However, it likely generally anticipates the architectural context of DSL systems with multiple latency paths, which forms the basis for the resource sharing problem addressed by US8276048B2.

3. US20060088054A1

• Full Citation: US20060088054A1, "Resource sharing in a telecommunications environment"
• Publication/Filing Date: Priority Date: 2004-10-12, Publication Date: 2006-04-27
• Brief Description: This appears to be a published application related to US8276048B2, as it shares the same priority date and a similar title. It likely describes the same or very similar subject matter concerning memory and processing power sharing among latency paths in a telecommunications transceiver. This is an earlier publication of the same invention.
• Potential Anticipated Claim(s): Given it shares the same priority date and likely describes the same invention, it would anticipate all claims of US8276048B2 if it were prior art. However, since it's a related application with the same priority date, it typically wouldn't be considered prior art to itself under 35 U.S.C. § 102, but rather an earlier publication of the same invention.

4. US7657818B2

• Full Citation: US7657818B2, "Dynamic minimum-memory interleaving"
• Publication/Filing Date: Priority Date: 2005-06-22, Publication Date: 2010-02-02
• Brief Description: This patent describes methods for dynamic minimum-memory interleaving, which is directly relevant to the memory allocation for interleavers. While it has a later priority date than US8276048B2's priority date, it was published before US8276048B2 was granted. The core concept of optimizing interleaver memory use is highly relevant.
• Potential Anticipated Claim(s): This patent could potentially anticipate elements of claims 1 and 5 related to determining the amount of memory required by an interleaver/deinterleaver and allocating shared memory to them, particularly if the "dynamic minimum-memory interleaving" discloses methods that would make the allocation steps obvious.

5. US9264075B2

• Full Citation: US9264075B2, "Dynamic buffer partitioning"
• Publication/Filing Date: Priority Date: 2011-09-09, Publication Date: 2016-02-16
• Brief Description: This patent describes dynamic buffer partitioning, which is conceptually similar to dynamic memory allocation or sharing. While it has a much later priority date than US8276048B2, it is cited as prior art. This suggests that the concept of dynamic buffer management, especially in a communication context, is a relevant area for comparison.
• Potential Anticipated Claim(s): Given its later priority date, it would not anticipate US8276048B2 under 35 U.S.C. § 102. It is cited as prior art by examiner, but the priority date of US8276048B2 is October 12, 2004, which precedes the priority date of US9264075B2.

6. US7085285B2

• Full Citation: US7085285B2, "xDSL communications systems using shared/multi-function task blocks"
• Publication/Filing Date: Priority Date: 2000-03-01, Publication Date: 2006-08-01
• Brief Description: This patent describes xDSL communication systems utilizing shared or multi-function task blocks. This is highly relevant as it addresses the concept of sharing resources (task blocks) in DSL systems, which is a core theme of US8276048B2. The "task blocks" could encompass framer, coder, and interleaver functionalities.
• Potential Anticipated Claim(s): This patent could potentially anticipate claims 1 and 5, particularly the concept of a transceiver allocating shared resources (like memory or processing modules) to different functional blocks (like interleavers/deinterleavers or coders/decoders) within a telecommunications environment, especially DSL.

7. WO2001045340A1

• Full Citation: WO2001045340A1, "Bit allocation method in a multicarrier system"
• Publication/Filing Date: Priority Date: 1999-12-16, Publication Date: 2001-06-21
• Brief Description: This international publication describes a bit allocation method in a multicarrier system. While primarily focused on bit allocation, which is a different aspect of resource management than memory or processing power, efficient bit allocation often goes hand-in-hand with effective utilization of other system resources. Its relevance might lie in how different data rates (resulting from bit allocation) influence the requirements for interleaving and coding, and thus the memory/processing needed.
• Potential Anticipated Claim(s): This patent might generally anticipate the concept of adjusting system parameters (like memory or processing allocation) based on communication parameters (like data rate), as mentioned in the broader scope of US8276048B2's functionality, especially in claims concerning parameter determination and allocation.

8. US6707822B1

• Full Citation: US6707822B1, "Multi-session asymmetric digital subscriber line buffering and scheduling apparatus and method"
• Publication/Filing Date: Priority Date: 2000-01-07, Publication Date: 2004-03-16
• Brief Description: This patent discusses buffering and scheduling for multi-session ADSL. Buffering is intrinsically linked to memory management, and scheduling relates to resource allocation over time. The concept of managing resources for multiple sessions in a DSL environment directly relates to US8276048B2's aim of sharing resources across multiple latency paths for different applications.
• Potential Anticipated Claim(s): This patent could potentially anticipate claims 1 and 5, particularly the aspects related to allocating shared memory to interleavers/deinterleavers in a DSL transceiver, especially where the allocation is influenced by managing multiple data streams or sessions with varying requirements.

9. US6381728B1

• Full Citation: US6381728B1, "Partitioned interleaver memory for map decoder"
• Publication/Filing Date: Priority Date: 1998-08-14, Publication Date: 2002-04-30
• Brief Description: This patent specifically describes a "partitioned interleaver memory." This is highly relevant as US8276048B2 discusses sharing memory for interleavers/deinterleavers. The concept of partitioning memory for interleaving functions is a direct precursor to the shared memory allocation described in US8276048B2.
• Potential Anticipated Claim(s): This patent directly anticipates claims 1 and 5, specifically the concept of allocating memory to an interleaver or deinterleaver, and the idea of having dedicated (partitioned) memory sections for these functions, which US8276048B2 extends to shared and dynamically allocated memory.

10. US5063533A

• Full Citation: US5063533A, "Reconfigurable deinterleaver/interleaver for block oriented data"
• Publication/Filing Date: Priority Date: 1989-04-10, Publication Date: 1991-11-05
• Brief Description: This patent describes a reconfigurable deinterleaver/interleaver, which highlights the ability to adapt interleaver characteristics. While not explicitly mentioning shared memory in the context of US8276048B2, the concept of reconfigurability is foundational to dynamically allocating shared resources based on changing communication conditions.
• Potential Anticipated Claim(s): This patent could potentially anticipate the "determining an amount of memory required by the interleaver" and the subsequent allocation based on parameters, as a reconfigurable interleaver would inherently imply such a determination and adjustment of its operational parameters, which could impact memory requirements.

11. US5898710A

• Full Citation: US5898710A, "Implied interleaving, a family of systematic interleavers and deinterleavers"
• Publication/Filing Date: Priority Date: 1995-06-06, Publication Date: 1999-04-27
• Brief Description: This patent describes a family of systematic interleavers and deinterleavers, focusing on the implementation aspects of these modules. While not explicitly about shared memory, it contributes to the general understanding and design of interleavers and deinterleavers, which are the core components for which memory is shared in US8276048B2.
• Potential Anticipated Claim(s): This patent may anticipate the basic functionality of the interleaver and deinterleaver modules themselves, as referenced in claims 1 and 5, by providing a foundational understanding of their design and operation.

12. US5898698A

• Full Citation: US5898698A, "Multiple codeword interleaver method and apparatus"
• Publication/Filing Date: Priority Date: 1996-09-24, Publication Date: 1999-04-27
• Brief Description: This patent specifically describes a "multiple codeword interleaver," which is highly relevant to handling multiple data streams or applications, similar to the multiple latency paths in US8276048B2. Managing multiple codewords often implies efficient use of memory and processing.
• Potential Anticipated Claim(s): This patent could anticipate claims 1 and 5, particularly the aspects concerning interleaving a "first plurality of RS coded data bytes" and the underlying mechanisms for handling multiple data streams requiring interleaving, which would inherently involve memory management for those streams.

This analysis focuses on the explicit citations provided within the US8276048B2 patent document and their direct relevance to the claims and disclosed invention.