Obviousness

Under 35 U.S.C. § 103, a patent claim is obvious if "the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains." (35 U.S.C. § 103). To establish obviousness, a combination of prior art references must teach all elements of the claims, and there must be a motivation for a person having ordinary skill in the art (PHOSITA) to combine these references with a reasonable expectation of success.

The present invention, US patent 8276048B2, titled "Resource sharing in a telecommunications environment," generally relates to sharing memory and processing resources within a transceiver, particularly for interleavers/deinterleavers and coders/decoders, and allocating these resources based on application requirements, as well as exchanging information about these capabilities between transceivers.

Identification of Prior Art References for Combination:

From the "Prior Art" section of US8276048B2, the following references are particularly relevant:

1. U.S. Pat. No. 6,775,320 (US6775320B1): Titled "Method and a multi-carrier transceiver supporting dynamic switching between active application sets" (Assigned to Aware, Inc., the original assignee of US8276048B2). US8276048B2 explicitly states in its background that "U.S. Pat. Nos. 6,775,320 and 6,778,596 describe DSL systems supporting multiple applications and multiple framer/coder/interleaver FCI blocks (an FCI block is also referred to as a latency path)." This reference teaches DSL systems handling multiple applications with varying transmission requirements (e.g., data rate, latency, bit error rate) using multiple FCI blocks. It also describes transferring "communication parameters" between modems for configuration. [cite: US8276048B2, Description, BACKGROUND, Col 1, lines 52-57; Description, DETAILED DESCRIPTION, Col 4, lines 45-55].
2. U.S. Pat. No. 7,085,285 (US7085285B2): Titled "xDSL communications systems using shared/multi-function task blocks" (Assigned to Realtek Semiconductor Corp.). This patent explicitly teaches the use of shared and multi-function task blocks in xDSL communication systems, which can perform various functions including interleaving, de-interleaving, encoding, and decoding, and that memory can be shared within these blocks. [cite: US8276048B2, Citations, US7085285B2].
3. U.S. Pat. No. 6,381,728 (US6381728B1): Titled "Partitioned interleaver memory for map decoder" (Assigned to Qualcomm Incorporated). This reference teaches a memory system for an interleaver that employs a partitioned memory scheme. [cite: US8276048B2, Citations, US6381728B1].

(Note regarding US6778596 vs. US6778589: The background of US8276048B2 explicitly references US Pat. Nos. 6,775,320 and 6,778,596. However, the formal "Citations" list on the Google Patents page for US8276048B2 lists US6775320B1 and US6778589B1. Adhering strictly to the instruction to "interpret patent numbers and identifiers literally" and "use the results from the Prior Art section of this page," US6778589B1 is the cited patent. However, its title, "Symbol synchronous device and frequency hopping receiver," suggests it is less relevant to resource sharing in DSL than the content described in the background of US8276048B2 for US6778596. For the purpose of this obviousness analysis, the detailed description of prior art found within the background section of US8276048B2 regarding US6775320 and US6778596 is taken as authoritative for the teachings of those patents, and US7085285B2 and US6381728B1 are drawn from the explicit citations list due to their clear relevance to the claimed subject matter.)

Motivation to Combine:

A person having ordinary skill in the art (PHOSITA) in telecommunications, facing the challenge of increasing memory and processing power requirements for supporting multiple latency paths and diverse applications in DSL systems (as identified in the background of US8276048B2), would be highly motivated to combine the teachings of these prior art references. The motivation would be to enhance the efficiency, flexibility, and cost-effectiveness of DSL transceivers by:

• Dynamically supporting multiple applications with varying quality-of-service (QoS) requirements (latency, BER, data rate), as taught by US6775320B1.
• Overcoming the limitations of dedicated, fixed-resource architectures by sharing hardware resources, specifically memory for interleavers/deinterleavers and processing power for coders/decoders, as suggested by the problem statement in US8276048B2 and directly taught by US7085285B2.
• Utilizing memory more efficiently for interleaving operations through partitioning or sharing, as taught by US6381728B1.
• Enabling interoperability and optimal configuration between transceivers by communicating their resource capabilities, building on the parameter exchange concepts in US6775320B1.

Obviousness Analysis of Claim 1 of US8276048B2:

Claim 1: "A system that allocates shared memory comprising: a transceiver that is capable of: transmitting or receiving a message during initialization specifying a maximum number of bytes of memory that are available to be allocated to an interleaver; determining an amount of memory required by the interleaver to interleave a first plurality of Reed Solomon (RS) coded data bytes within the shared memory; allocating a first number of bytes of the shared memory to the interleaver to interleave the first plurality of Reed Solomon (RS) coded data bytes for transmission at a first data rate, wherein the allocated memory for the interleaver does not exceed the maximum number of bytes specified in the message; allocating a second number of bytes of the shared memory to a deinterleaver to deinterleave a second plurality of RS coded data bytes received at a second data rate; and interleaving the first plurality of RS coded data bytes within the shared memory allocated to the interleaver and deinterleaving the second plurality of RS coded data bytes within the shared memory allocated to the deinterleaver, wherein the shared memory allocated to the interleaver is used at the same time as the shared memory allocated to the deinterleaver."

1. "transmitting or receiving a message during initialization specifying a maximum number of bytes of memory that are available to be allocated to an interleaver;"

   • US6775320B1 teaches multi-carrier transceivers that support dynamic switching between active application sets and the transfer of communication parameters between modems during initialization or SHOWTIME for configuration. [cite: US8276048B2, Description, DETAILED DESCRIPTION, Col 4, lines 45-55]. A PHOSITA, motivated to optimize resource allocation in a system with shared resources (as taught by US7085285B2), would find it obvious to include information about a transceiver's available shared memory for an interleaver in such configuration messages. This enables the remote transceiver to make informed decisions for allocating shared resources, ensuring efficient utilization and preventing over-allocation.

2. "determining an amount of memory required by the interleaver to interleave a first plurality of Reed Solomon (RS) coded data bytes within the shared memory;"

   • The background of US8276048B2 itself highlights that different applications (e.g., video, voice) have different transmission requirements for latency and BER, and that interleaving provides error correcting capability, consuming a large amount of memory. [cite: US8276048B2, Description, BACKGROUND, Col 1, lines 58-67]. US6775320B1 describes different FCI blocks having different capabilities depending on application requirements. [cite: US8276048B2, Description, BACKGROUND, Col 1, lines 52-57]. The calculation of interleaver memory (N*D bytes for codeword size N and interleaver depth D) is a fundamental engineering principle in the design of interleaving systems for Forward Error Correction (FEC). Thus, determining the required memory for interleaving RS coded data to meet specific application requirements would be obvious to a PHOSITA.

3. "allocating a first number of bytes of the shared memory to the interleaver to interleave the first plurality of Reed Solomon (RS) coded data bytes for transmission at a first data rate, wherein the allocated memory for the interleaver does not exceed the maximum number of bytes specified in the message;"

   • US7085285B2 explicitly teaches xDSL systems using "shared/multi-function task blocks" where "memory can be shared" among functions, including interleaving. [cite: US8276048B2, Citations, US7085285B2]. US6381728B1 teaches partitioned memory for interleaver operations, demonstrating that memory can be divided and assigned for interleaving. [cite: US8276048B2, Citations, US6381728B1]. A PHOSITA, seeking to implement dynamic resource allocation in a multi-application DSL system (as taught by US6775320B1) using shared memory (as taught by US7085285B2 and US6381728B1), would find it obvious to allocate a portion of that shared memory to an interleaver based on determined requirements, while ensuring that the allocation respects the communicated maximum available memory. This is a standard resource management practice. The allocation based on data rate is a known method for optimizing performance for different applications, as suggested by US6775320B1.

4. "allocating a second number of bytes of the shared memory to a deinterleaver to deinterleave a second plurality of RS coded data bytes received at a second data rate;"

   • As with interleaving, US7085285B2 teaches that shared/multi-function task blocks in xDSL systems can also perform de-interleaving and that memory can be shared for these functions. [cite: US8276048B2, Citations, US7085285B2]. Since DSL transceivers are full-duplex devices, receiving data (and thus deinterleaving it) is a complementary operation to transmitting data (interleaving it). It would be obvious for a PHOSITA to allocate another portion of the same shared memory to a deinterleaver for received data, using the same principles of dynamic allocation based on data rate and other communication parameters.

5. "interleaving the first plurality of RS coded data bytes within the shared memory allocated to the interleaver and deinterleaving the second plurality of RS coded data bytes within the shared memory allocated to the deinterleaver, wherein the shared memory allocated to the interleaver is used at the same time as the shared memory allocated to the deinterleaver."

   • DSL systems, as described in US6775320B1 and generally understood in the art, are full-duplex communication systems, meaning they transmit and receive simultaneously. If shared memory is allocated to both an interleaver (for transmit) and a deinterleaver (for receive) within such a system (as enabled by US7085285B2 and US6381728B1), their concurrent operation using their respective allocated portions of the shared memory is an inherent and expected functional aspect of a transceiver. This simultaneous use would be obvious to any PHOSITA designing a full-duplex communication system with shared resources.

Obviousness Analysis of Dependent Claims 2-4 (and 6-8):

Claims 2-4 and 6-8 depend on Claims 1 and 5, respectively, specifying that the "determining is based on an impulse noise protection requirement," "a latency requirement," or "a bit error rate requirement."

• US6775320B1 and the background of US8276048B2 clearly establish that DSL systems carry applications with diverse transmission requirements, including data rate, latency, and bit error rate (BER). [cite: US8276048B2, Description, BACKGROUND, Col 1, lines 52-57]. The background further details how different applications (e.g., video, voice) have distinct latency and BER tolerances. Impulse noise protection is a known benefit of interleaving, directly related to the interleaver depth and coding scheme. [cite: US8276048B2, Description, DETAILED DESCRIPTION, EXAMPLE #1, Col 5, lines 30-35]. A PHOSITA would routinely account for these critical QoS parameters when determining the necessary interleaver/deinterleaver memory and coding configuration (e.g., N, D, R for Reed-Solomon coding) to ensure the application requirements are met. Therefore, determining memory allocation based on impulse noise protection, latency, or bit error rate requirements would be an obvious design choice for a PHOSITA.

Conclusion:

The combination of US6775320B1, US7085285B2, and US6381728B1 would have rendered the claims of US8276048B2 obvious to a person having ordinary skill in the art at the time of the invention. The motivation to combine these references stems from the clear industry need to efficiently manage and allocate resources in DSL transceivers supporting multiple applications with diverse quality-of-service requirements, as explicitly articulated in the background and summary of US8276048B2 itself. The combination of these references teaches all the elements of the independent claims and their dependent claims, and a PHOSITA would have a clear rationale and reasonable expectation of success in combining these known elements for improved resource management in telecommunication systems.