Obviousness

The following analysis evaluates the obviousness of US Patent 8,060,644 under 35 U.S.C. § 103, considering prior art cited within the patent. The Person Having Ordinary Skill in the Art (PHOSITA) at the priority date of May 11, 2007, would be knowledgeable in network protocols (e.g., TCP/IP), network interface card (NIC) design, direct memory access (DMA), operating system (OS) memory management, and techniques for offloading network protocol processing to specialized hardware.

I. Obviousness of Independent Claim 1

Independent Claim 1 generally describes a method for an intelligent network adaptor to perform protocol processing for a stateful connection, obtain application data, indicate a receive window to a peer, place application data directly into a host memory application buffer (bypassing OS buffers), and increase the receive window based on the application consuming data from this application buffer.

Combination 1: US6434620B1 (Alacritech) + US6757746B2 (Alacritech) + US7089289B1 (IBM)

1. US6434620B1 (Alacritech, "TCP/IP offload network interface device"): This patent discloses an "intelligent network adaptor" or TCP Offload Engine (TOE) that performs TCP/IP protocol processing, offloading these tasks from the host CPU. This establishes the basic intelligent network adaptor and protocol offload functionality.
2. US6757746B2 (Alacritech, "Obtaining a destination address so that a network interface device can write network data without headers directly into host memory"): This reference teaches a network interface device's ability to directly write "network data without headers... into host memory" by obtaining a destination address. This clearly anticipates the "direct data placement" (DDP) or "zero-copy" aspect of claim 1, where application data bypasses intermediate OS buffers and goes straight to application memory.
3. US7089289B1 (IBM, "Mechanisms for efficient message passing with copy avoidance in a distributed system using advanced network devices"): This patent further details "copy avoidance" techniques using "advanced network devices" to achieve efficient message passing, supporting the direct data placement concept.

Motivation for Combination:
A PHOSITA, aiming to address the challenges of high-speed communication identified in the '644 patent's background (high packet arrival rates, memory bandwidth for copying, and achieving low latency with reduced host processing), would be motivated to combine the TCP/IP offload capabilities of the '643 patent with the direct data placement (zero-copy) techniques of the '746 and '289 patents. The objective of such a combination is to eliminate redundant data copying from OS buffers to application buffers, thereby reducing CPU cycles and improving end-to-end latency.

Regarding the receive window mechanism, TCP's receive window is a fundamental flow control mechanism that signals the sender how much buffer space is available at the receiver to prevent data overflow. When a TOE offloads TCP processing and simultaneously performs direct data placement into application buffers, the logical next step for a PHOSITA would be to tie the receive window advertisement to the actual consumption of data by the application from those buffers. This ensures that the flow control truly reflects the application's capacity to process data, rather than just the adaptor's or OS's temporary buffering capabilities. The '644 patent itself highlights this motivation: "If the TCP window flow control is made dependent on this flow control scheme, such as by basing the TCP window size on the number of credits available to the intelligent network adaptor, it is possible to perform end-to-end flow control with the application as terminus, as opposed to with the intelligent network adaptor or operating system buffers as terminus." This describes an optimization to existing flow control mechanisms, making the extension obvious to a PHOSITA seeking to optimize network performance.

II. Obviousness of Independent Claim 5

Independent Claim 5 extends Claim 1 by specifying how to handle application buffers that are larger than the maximum memory amount allowed by the connection-oriented protocol for flow control (e.g., 1 GB for TCP). It dictates that the host exposes only a portion or "window" of this large application buffer to the intelligent network adaptor at any given time, with this portion being no larger than the protocol's flow control limit.

Combination 2: Combination 1 (US6434620B1 + US6757746B2 + US7089289B1) + US6460080B1 (Intel) + General Knowledge of Ring Buffers/Sliding Windows

1. Combination 1 (as detailed above): Provides the baseline of an intelligent network adaptor with TCP offload and direct data placement.
2. US6460080B1 (Intel, "Credit based flow control scheme over virtual interface architecture for system area networks"): This patent discloses a "credit based flow control scheme". While in a different architectural context (virtual interface), the core concept of using a credit system to manage available buffer space and regulate a sender's transmission rate is directly analogous to TCP's window-based flow control. A PHOSITA would recognize the applicability of credit-based systems to other network flow control scenarios.
3. General Knowledge of Ring Buffers/Sliding Windows: By 2007, ring buffers (circular buffers) and sliding window mechanisms were well-established and widely known data structures and techniques in computer science and networking. They were commonly used to manage continuous data streams within fixed-size memory regions or to segment larger logical buffers for interaction with protocols having limited window sizes. The '644 patent itself describes this: "An even larger receive memory can be utilized by dividing the receive memory into smaller sized 'windows' and proceeding through the windows in sequence... In this manner, it is possible to expose 1 GB of memory at a time, and to move through a large memory area by 'sliding' the exposed receive window as the data placement progresses." It further states: "It is therefore possible to visualize the operation as a ring buffer 413". These descriptions indicate that these concepts were known solutions for managing large buffers with fixed-size protocol windows.

Motivation for Combination:
A PHOSITA confronted with the challenge of utilizing very large application receive buffers (exceeding typical TCP window limits) while still maintaining efficient end-to-end flow control with direct data placement would be motivated to combine the established principles from Combination 1 with known buffer management strategies. The '644 patent's own problem statement implies the need for such a solution. Integrating the credit-based flow control concept from the '080 patent with the well-understood "sliding window" or "ring buffer" mechanism (as described in the '644 patent) would be an obvious design choice. This approach allows the host to conceptually "slide" a smaller, protocol-compliant window across the larger application buffer, exposing only a manageable portion to the network adaptor at any given time. As the application consumes data from the current window, credits are implicitly or explicitly returned (akin to the '080 patent), allowing the window to advance and expose new memory, thereby enabling large transfers without exceeding protocol limitations.

III. Obviousness of Dependent Claims 2-4 and 6-14

Many dependent claims introduce details that would be considered either inherent to the core concepts of claims 1 and 5, or obvious optimizations and design choices for a PHOSITA.

• Claim 2 (reducing receive window based on data placement): This is a fundamental principle of window-based flow control; as data occupies buffer space, available space (and thus the window) decreases. This is an inherent and obvious action.
• Claim 3 (maintaining receive window credits): This is a common implementation detail for managing window-based flow control, explicitly taught by references like US6460080B1.
• Claim 4 (placing data to OS buffer as fallback): The '644 patent itself describes an "adaptive copy avoidance" scheme where data may be placed in OS buffers if application buffers aren't available, then copied later. This is a practical and obvious fallback mechanism to ensure data is not dropped when direct placement is not immediately possible. The impact on the receive window (reduction if stored in OS buffers) is a straightforward application of flow control principles.
• Claim 6 (host maintaining ring structure): As discussed for Claim 5, ring buffers are a well-known data structure for managing continuous data streams in memory.
• Claim 7 (plurality of overlapping windows): This is a description of a sliding window on a larger buffer, a known technique for stream processing and memory management.
• Claim 8 (producer/consumer pointers in a ring structure): This is the standard operational model for a ring buffer, where a producer (adaptor) adds data and a consumer (application) removes it, managing their positions with pointers.
• Claim 9 (releasing credits, adaptor generating window): This reiterates the credit-based flow control mechanism, where the application's consumption frees up "credits" that are then used by the adaptor to expand the receive window, directly applying the principles from US6460080B1 to the application-driven flow.
• Claim 10 (accumulating and bunching credits): This is a standard network optimization to reduce overhead by batching small updates into fewer, larger messages. The patent explicitly states this can "minimize the number of update messages being communicated".
• Claim 11 (adaptor accumulating notifications to moderate host notifications): Moderating notification rates (e.g., interrupts) to the host CPU is a well-known technique to reduce host processing load, particularly in high-speed networking contexts, and is directly stated as a goal in the '644 patent.
• Claim 12 (constraining producer pointer): This is a fundamental safety mechanism in any buffer management system, especially ring buffers, to prevent the producer from overwriting data that the consumer has not yet processed, ensuring data integrity and correct flow control.
• Claim 13 (decrementing receive window credits): As the adaptor places data, it consumes buffer space, which logically corresponds to decrementing available "credits" or shrinking the receive window advertised to the peer. This is the inverse operation of Claim 9 and an inherent part of the credit/window-based flow control.
• Claim 14 (spatially reordering out-of-order data in the application buffer): Reassembling out-of-order data segments is a standard function of reliable transport protocols like TCP. Performing this reassembly directly in the application buffer is a logical extension of direct data placement, aiming to further reduce copies and latency by leveraging the destination buffer itself for reordering. The patent describes this as a possible implementation: "The intelligent network adaptor may place received out-of-order data directly in the buffer 409, and therefore perform data re-assembly in the buffer 409 itself".

In conclusion, the dependent claims largely describe obvious implementation details, optimizations, or well-known technical concepts that a PHOSITA would readily integrate when developing an intelligent network adaptor system with end-to-end direct data placement and flow control. The motivations consistently center around improving efficiency, reducing host overhead, and ensuring robust data handling in high-speed network environments, all of which were recognized challenges in the prior art.