Prior art

US Patent 7930575 identifies one related art, Japanese Laid-Open Patent Publication No. 2005-11166, in its background section. This reference describes a technique involving a standby control circuit that maintains power to an information holding circuit within a peripheral circuit module while shutting down power to the CPU and other peripheral circuits. Upon an interrupt request, power to the CPU and peripheral module is restored, and evacuated information is returned, allowing for reduced standby current and high-speed restoration via interrupt.

While the full text of Japanese Laid-Open Patent Publication No. 2005-11166 is not provided in the prompt, based on the description within US7930575, this prior art appears to anticipate aspects of claims related to:

• Claim 1 (and potentially other claims that involve power shutdown and restoration for a CPU and peripheral circuits): The Japanese patent describes a system where power is selectively shut down to a CPU and peripheral circuits while maintaining power to an information holding circuit, and then restored upon an interrupt. This directly relates to the core concept of controlled power shutdown and restoration as claimed in US7930575.

The patent 7930575 distinguishes itself from this prior art by addressing specific drawbacks, such as the potential for evacuated register values to change if interrupts are accepted before power shutdown, the need to prohibit interrupts during evacuation, and the increased circuit scale due to dedicated logic and wiring for information holding and preventing current flow. The present invention (US7930575) aims to overcome these by continuously executing information evacuation and power shutdown using a microprogram, thereby avoiding interrupt processing between these steps and preventing data changes before shutdown. It also states that existing wirings can be used, minimizing additional logic circuits and wirings.