Obviousness

Obviousness Analysis under 35 U.S.C. § 103

To establish obviousness under 35 U.S.C. § 103, it must be demonstrated that the claimed invention as a whole would have been obvious to a person having ordinary skill in the art at the time of the invention. This requires identifying a motivation to combine prior art references to arrive at the claimed invention with a reasonable expectation of success. Motivation to combine can arise from the nature of the problem, the knowledge of those skilled in the art, or the teachings of the prior art references themselves.

The primary objective of US patent 7930575 is to provide a microcontroller capable of easily and rapidly evacuating and restoring necessary program information during a power shutdown mode, or a mode where internal operating voltage is lowered, to suppress current consumption while allowing program continuation.

Combination 1: Japanese Laid-Open Patent Publication No. 2005-11166 in view of general knowledge in the art

Prior Art:
Japanese Laid-Open Patent Publication No. 2005-11166 discloses a technique for suppressing current consumption in a standby mode. It describes a standby control circuit that continues to supply power to an information holding circuit (e.g., for registers in a peripheral circuit module) while shutting down power to the CPU and other peripheral circuits. Upon an external interrupt request, power is resumed to the CPU and peripheral modules, evacuated information is restored, and an interrupt processing is performed, allowing for reduced standby current and high-speed restoration.

Analysis of Obviousness:
Claim 1 of US 7930575 details a microcontroller where, upon a power shutdown factor, a power supply control unit signals the CPU, which then activates a power shutdown microprogram to evacuate information to an information holding unit. After evacuation, the CPU signals completion, and the power supply control unit instructs the power supply unit to shut down power to the CPU.

Japanese Laid-Open Patent Publication No. 2005-11166 already teaches the core concept of maintaining power to an information holding unit while shutting down power to the CPU and peripheral circuits to reduce standby current and enable quick restoration. A person having ordinary skill in the art (POSITA) at the time of the invention would have been motivated to implement this power shutdown and restoration sequence in a more controlled and efficient manner.

The use of a "power shutdown microprogram" to evacuate information and an "evacuation completed signal" to control the power shutdown, as claimed in US 7930575, would have been an obvious design choice to a POSITA. Microprograms are standard control programs within a CPU for executing commands and managing internal resources. Given the objective of ensuring that necessary information is reliably saved before power is cut, a POSITA would recognize that a dedicated, atomic sequence, such as a microprogram, would prevent data corruption or inconsistencies that could arise if interrupts were allowed during the evacuation process. This is a known technique to ensure data integrity during critical operations.

Furthermore, the concept of signaling completion of a task (like data evacuation) to a control unit before initiating the next dependent action (like power shutdown) is a fundamental principle in embedded system design and would be considered common sense to a POSITA. This provides a robust handshake mechanism, improving system reliability.

Therefore, the combination of the power management scheme taught by Japanese Laid-Open Patent Publication No. 2005-11166 with the routine application of microprogramming techniques and basic control signaling, known to a POSITA for ensuring data integrity and reliable system operation, would render Claim 1 obvious. The motivation would be to enhance the reliability and efficiency of the existing power shutdown and restoration process by ensuring proper data handling and sequential operation.

Combination 2: Japanese Laid-Open Patent Publication No. 2005-11166 in view of US 7716505 B2

Prior Art:

• Japanese Laid-Open Patent Publication No. 2005-11166: As described above, this reference teaches a standby control circuit that maintains power to an information holding circuit while cutting power to the CPU and peripherals, enabling quick restoration upon interrupt.
• US 7716505 B2 (filed October 18, 2006, published May 18, 2010): This patent describes a power control method for a portable electronic device. It involves setting the device to a "deep sleep mode," transferring data from volatile memory to non-volatile memory, and then turning off the power supply unit, except for maintaining sufficient power for restoration. Although it mentions transferring to non-volatile memory, the general concept of evacuating data from an active processing unit to a holding unit before power down is relevant.

Analysis of Obviousness:
Claim 1 of US 7930575 describes evacuating information from the CPU to an information holding unit before shutting down power to the CPU. Japanese Laid-Open Patent Publication No. 2005-11166 establishes the benefit of selectively powering down components while retaining crucial information for fast wake-up. US 7716505 B2 reinforces the practice of saving data from active memory before entering a low-power state.

A POSITA, seeking to further optimize the power saving and restoration process described in Japanese Laid-Open Patent Publication No. 2005-11166, would be motivated to explicitly manage the data evacuation process more robustly. Japanese Laid-Open Patent Publication No. 2005-11166 already mentions "holding the value of a register contained in a peripheral circuit module," which implies data evacuation. US 7716505 B2 explicitly teaches "transferring data accessed from the volatile memory to a non-volatile memory" before turning off the power unit.

Combining these teachings, a POSITA would recognize the advantage of using a microprogram (as a known technique for controlled internal CPU operations) to orchestrate the evacuation of critical program information (like PC, PSW, SP as mentioned in US 7930575) to the information holding unit before the CPU's power is cut. The motivation would be to ensure that the "information necessary in proceeding with the program" is reliably and completely saved, building upon the general concept of data retention for quick restoration found in Japanese Laid-Open Patent Publication No. 2005-11166 and the explicit data transfer steps in US 7716505 B2. The use of an "evacuation completed signal" would be a natural control mechanism to ensure the data transfer is finished before power-off, thereby enhancing system reliability.

Conclusion:

The core inventive concepts of US 7930575, particularly those in independent claims 1, 4, 16, and 17, appear to build upon existing prior art related to power management and data retention in microcontrollers. The specific mechanisms, such as the use of microprograms for controlled evacuation and restoration, and dedicated signaling, represent logical advancements or straightforward engineering choices that a person having ordinary skill in the art would likely have made to improve efficiency and reliability in power-saving modes, given the problems and known techniques in the field.