Obviousness

Obviousness Analysis under 35 U.S.C. § 103

A patent claim is obvious if "the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains." (35 U.S.C. § 103). This analysis requires considering the scope and content of the prior art, differences between the prior art and the claims, the level of ordinary skill in the art, and any secondary considerations of non-obviousness.

US patent 7882320, titled "Multi-processor flash memory storage device and management system," addresses limitations of single-processor Flash storage devices, specifically RAM and data bus contentions that hinder scalability and performance (Description, BACKGROUND OF THE INVENTION). The patent proposes a distributed architecture with multiple microprocessor units, each having dedicated RAM and dedicated bus connections to Flash device configurations, managed by a dataflow controller (Abstract; Claim 1).

Prior Art References and Potential Combinations:

The patent itself identifies several prior art references in its "Cited By" and "Citations" sections. For an obviousness analysis, we will focus on the "Citations" as these are the references considered by the Examiner during prosecution.

The inventor notes that "The present invention is a continuation-in-part (CIP) to a U.S. patent application Ser. No. 11/439,619, filed May 23, 2006 and entitled “Hybrid Solid State Disk Drive with Controller”, to a U.S. patent application Ser. No. 11/439,620, filed May 23, 2006 and entitled “Software Program for Managing and Protecting Data Written to a Hybrid Solid State Disk Drive”, and to a U.S. patent application Ser. No. 11/439,615, filed on May 23, 2006 and entitled “Methods for Managing Data Writes and Reads to a Hybrid Solid State Disk Drive”; disclosures of which are incorporated in their entireties at least by reference." These related applications, while part of the same inventive entity, are generally considered prior art for obviousness purposes to the extent that they disclose subject matter earlier than the filing date of the CIP, subject to certain "by another" considerations for pre-AIA cases. Since US7882320 was filed in 2008, it falls under pre-AIA rules for prior art. For a reference to not be "by another" and thus not qualify as prior art, the disclosure in the reference must reflect the work of the entire inventive entity of the challenged patent claim. Any incongruity in the inventive entity between the inventors of a prior reference and the inventors of a patent claim renders the prior disclosure "by another", regardless of whether inventors are subtracted from or added to the patent. However, the prior art listed below were cited by the examiner, indicating they were considered "by another" or otherwise qualifying prior art.

Let's examine some of the cited prior art and consider combinations:

1. US20070276994A1 (Caulkins): "Methods for managing data writes and reads to a hybrid solid-state disk drive"

• Disclosure: This publication, also by Jason Caulkins (the inventor of US7882320), describes a hybrid solid-state disk drive that uses volatile RAM for caching data and a non-volatile Flash memory for long-term storage. It emphasizes using RAM to minimize writes to Flash to preserve Flash lifespan and includes mechanisms for writing data from RAM to Flash upon power down, interruption, or when RAM cache is full (Description,). It also mentions wear leveling (Description,).
• Relevance to US7882320: This reference already establishes the concept of a hybrid solid-state drive with RAM caching for Flash writes, wear leveling, and data protection on power loss, which are key aspects of US7882320 (Description, FIG. 5, FIG. 6). The primary difference is that US20070276994A1 describes a single-processor architecture, which US7882320 aims to improve upon.

2. US7103684B2 (Rose Steven W.): "Single-chip USB controller reading power-on boot code from integrated flash memory for user storage" (and related US7383362B2, US20080320214A1, US20090193184A1, US20090204732A1, US20090240873A1)

• Disclosure: These patents and applications (by Super Talent Electronics, Inc. and Steven W. Rose) generally describe single-chip controllers for Flash memory devices, often in the context of USB controllers or multimedia cards. They involve managing Flash memory for user storage and handling boot code. While not explicitly multi-processor, they show the state of the art in Flash memory management with a controller. US20080320214A1 specifically mentions a "Multi-Level Controller with Smart Storage Transfer Manager for Interleaving Multiple Single-Chip Flash Memory Devices," suggesting a level of sophistication in managing multiple Flash devices.

3. US20060031389A1 (Shimozono): "Storage system, computer system, and method of configuring storage system"

• Disclosure: This reference describes a storage system with multiple storage devices and a method for configuring them. While broad, it points to the general knowledge of combining and managing multiple storage units.

Obviousness Combinations:

A person having ordinary skill in the art (POSA) in 2008, when US7882320 was filed, would have been aware of the increasing demand for faster and more scalable Flash-based storage systems, as noted in the background of US7882320 (Description, BACKGROUND OF THE INVENTION). The limitations of single-processor Flash management systems due to RAM and data bus contentions would also have been apparent (Description, BACKGROUND OF THE INVENTION).

Combination 1: US20070276994A1 (Caulkins) in view of the general desire for scalability and performance in Flash storage.

• Rationale: US20070276994A1 already teaches a significant portion of the invention claimed in US7882320, including RAM caching, wear leveling, and data protection for Flash memory in a solid-state drive. The primary deficiency it highlights, which US7882320 aims to solve, is the bottleneck created by a single processor and shared bus in robust, enterprise-scale systems (Description, BACKGROUND OF THE INVENTION).
• Motivation to Combine/Modify: A POSA, faced with the recognized problem of performance degradation and scaling limitations in a single-processor Flash management system (as implicitly described by US20070276994A1 and explicitly by US7882320), would have been motivated to explore ways to distribute the processing load. It would have been obvious to a POSA to move from a single, complex processor to a distributed architecture using multiple, simpler processors to manage different Flash channels, thereby alleviating RAM and bus contentions. This is a common architectural approach to improve performance and scalability in computing systems. The patent itself states, "The inventor conceptualized and subsequently provided a Flash data storage device constructed using a distributive architecture that was less expensive to implement and had fewer RAM and bus contention issues than single processor devices. The result was a better performance relative to data management speeds including reads and writes" (Description, SUMMARY OF THE INVENTION). This statement suggests that the idea of a distributed architecture for improved performance was a known and desirable goal in the art.

Addressing specific claims:

• Claim 1: The core of Claim 1 involves a plurality of microprocessor units each with dedicated RAM, connected to Flash configurations, and a dataflow controller managing access and performing periodic data moves from RAM to Flash based on a threshold.
  • US20070276994A1 teaches the RAM caching, the movement of data from RAM to Flash when the cache is full or on power interruption, and updating tables. The motivation to distribute this functionality across multiple microprocessors, each with its dedicated RAM and Flash channel, would come from the desire to overcome the performance bottlenecks of a single processor system. The "dedicated bus connections to individual ones or multiples of the microprocessor units" is a direct solution to the "RAM and specific data bus contentions" identified as a problem in the prior art (Description, BACKGROUND OF THE INVENTION). The "dataflow controller" to manage these multiple units would be an obvious architectural component for coordinating a distributed system. The periodic comparison of valid data volume and moving oldest data (wear leveling) is an existing Flash management technique already taught in US20070276994A1.
• Claims 2, 3, 4, 8 (Flash Channel Configurations and Memory Types): These claims specify the Flash configurations (individual Flash channels, parallel/daisy-chained chips, NAND/Phase Change Memory). These are common and known configurations and types of Flash memory. A POSA would have known to implement Flash memory in various ways and with different technologies based on cost, performance, and density requirements. US7103684B2 and its related patents/applications demonstrate existing approaches to managing Flash memory devices and configurations.
• Claims 5, 6, 7 (Dataflow Controller Implementations): These claims describe the dataflow controller as an onboard microprocessor with dedicated RAM, a state machine, or integrated hardware with the host controller. These are standard implementation choices for controllers in data storage devices. A POSA would have understood that a controller's functions could be implemented in various forms depending on the system's complexity and performance needs.

Secondary Considerations of Non-obviousness:

The provided text does not contain information about secondary considerations such as commercial success, long-felt but unmet need (beyond the general problem statement), failure of others, unexpected results, or licensing activities that could support non-obviousness. While the patent identifies a "need for faster data management speeds" (Description, BACKGROUND OF THE INVENTION), the proposed solution of a distributed architecture is an obvious engineering choice for improving performance and scalability.

Conclusion:

Based on the available information, the core claims of US7882320, particularly Claim 1, appear to be obvious over US20070276994A1 (Caulkins) in combination with the general knowledge in the art regarding distributed architectures for overcoming performance bottlenecks in single-processor systems. The motivation for such a combination arises directly from the recognized limitations of single-processor Flash management systems and the widely understood benefits of distributing processing loads for improved scalability and performance. The dependent claims merely elaborate on known implementations of Flash memory and controller technologies.