Prior art — US Patent 7864816

US patent 7864816, titled "Integrated circuit for network delay and jitter testing," was filed on February 11, 2005, with a priority date of January 7, 2005. The patent describes an integrated circuit (IC) that can conduct network delay and jitter testing at the Media Access Control (MAC) level and above, aiming to minimize the burden on the device's Central Processing Unit (CPU). The IC includes ports with a packet generator to originate timestamped test packets, and a controller to calculate network delay and jitter based on these packets and their replies.

A thorough analysis under 35 U.S.C. § 102 for each of the 54 prior art citations would involve a detailed claim-by-claim mapping of every element of US7864816's claims against each reference. This level of detail is extensive and beyond the scope of this summary. However, based on the titles and abstracts of selected prior art, we can identify potential areas of anticipation for the core concepts of US7864816.

Below are details for some of the most relevant patent citations, chosen based on their titles' direct relevance to network delay, jitter, and timestamping, and their publication dates preceding the priority date of US7864816.

Selected Prior Art Citations for US7864816:

US5307354A
- Full Citation: U.S. Patent 5,307,354 to C. C. Lo, et al., "Method and apparatus for measuring end-to-end network delay and jitter using time-stamping packets"
- Publication/Filing Date: Filed September 15, 1992; Published April 26, 1994.
- Brief Description: This patent describes a method and apparatus for measuring end-to-end network delay and jitter by transmitting packets with timestamps from a sender to a receiver and calculating delay based on the timestamps and reception times. It uses a network management station (NMS) to coordinate tests and collect results from network elements.
- Potential Anticipation (35 U.S.C. § 102):
  - Claims 1, 16, 25, 40 (core concept of network delay calculation): The fundamental concept of using timestamped packets to measure network delay and jitter is directly taught. Specifically, the idea of originating a packet with a time of transmission/generation and using it with a reply packet to calculate delay is present. While US7864816 specifies an integrated circuit with a packet generator within a port, the core methodology of timestamping and delay calculation is anticipated.
  - Claims 6, 21, 30, 45 (jitter determination): The patent explicitly teaches determining network jitter from a plurality of network delays.
US5579308A
- Full Citation: U.S. Patent 5,579,308 to C. C. Lo, et al., "Method and apparatus for active measurement of network performance"
- Publication/Filing Date: Filed May 1, 1995; Published November 26, 1996.
- Brief Description: This patent describes an active measurement system for network performance that sends specially formatted test packets to measure various metrics, including delay and jitter. The system uses network management agents to perform measurements and report data back to a central station.
- Potential Anticipation (35 U.S.C. § 102):
  - Claims 1, 16, 25, 40 (active testing and delay measurement): The concept of actively injecting test packets into a network to measure performance metrics like delay and jitter is anticipated. The use of "specially formatted test packets" aligns with US7864816's packet generator originating packets with timestamps.
  - Claims 6, 21, 30, 45 (jitter determination): Similar to US5307354A, this patent teaches the measurement of jitter as a network performance metric.
US6452945B1
- Full Citation: U.S. Patent 6,452,945 to F. M. Vitenberg, "Method and apparatus for measuring network performance, loss, delay and jitter of packets"
- Publication/Filing Date: Filed June 21, 2000; Published September 17, 2002.
- Brief Description: This patent describes a system and method for measuring network performance characteristics, including packet loss, delay, and jitter. It involves sending test packets with timestamps and analyzing the timestamps of received packets and acknowledgment packets to determine performance metrics. The method allows for measurement of both one-way and two-way delay.
- Potential Anticipation (35 U.S.C. § 102):
  - Claims 1, 16, 25, 40 (comprehensive delay and jitter measurement): This patent directly teaches methods for measuring delay and jitter of packets using timestamps. The analysis of received and acknowledgment packets to determine various delay types (one-way, two-way) is a core aspect shared with US7864816.
  - Claims 2, 3, 4, 5, 17, 18, 19, 20, 26, 27, 28, 29, 41, 42, 43, 44 (specific delay calculation methods): The varying ways delay is calculated (e.g., based on receipt time, or timestamps within reply packets) are explicitly discussed.
  - Claims 6, 21, 30, 45 (jitter determination): The patent clearly addresses determining jitter based on delay measurements.
US6795450B1
- Full Citation: U.S. Patent 6,795,450 to T. S. Bell et al., "Network measurement of latency and jitter"
- Publication/Filing Date: Filed May 15, 2000; Published September 21, 2004.
- Brief Description: This patent describes a system and method for measuring network latency (delay) and jitter. It involves a "latency engine" that inserts timestamps into packets and uses these timestamps to calculate the time taken for packets to traverse the network. The system can be integrated into network devices.
- Potential Anticipation (35 U.S.C. § 102):
  - Claims 1, 16, 25, 40 (latency/delay and jitter measurement with timestamping): The core functionality of measuring network latency and jitter by inserting timestamps into packets and calculating based on these timestamps is strongly anticipated. The concept of a "latency engine" performing this function suggests an integrated hardware approach, which is a key aspect of US7864816's integrated circuit.
  - Claims 2, 3, 4, 5, 17, 18, 19, 20, 26, 27, 28, 29, 41, 42, 43, 44 (specific delay calculation methods): The methods of using timestamps for delay calculation would likely cover the various ways delay is determined in US7864816.
  - Claims 6, 21, 30, 45 (jitter determination): Jitter measurement is explicitly a focus of this patent.
US20030103493A1
- Full Citation: U.S. Patent Application Publication 2003/0103493 to K. B. Thompson, "Methods and systems for measuring network quality of service metrics using packet sampling"
- Publication/Filing Date: Filed November 27, 2001; Published June 5, 2003.
- Brief Description: This publication describes methods and systems for measuring network Quality of Service (QoS) metrics, including delay and jitter, by analyzing sampled packets. It details how network devices can monitor packet flows and collect statistics related to QoS.
- Potential Anticipation (35 U.S.C. § 102):
  - Claims 9, 22, 33, 46 (classifier and counter for packet properties/QoS): This reference teaches determining QoS metrics and monitoring packet flows, which aligns with US7864816's classifier and counter mechanisms to determine properties and count packets matching property definitions, especially concerning "one or more qualities of service for the packets of the first data" (Claims 10, 23, 34, 47).
  - Claims 1, 16, 25, 40 (general network testing context): While not as specific on timestamping and packet generation within a port as other references, it broadly anticipates the goal of integrated network devices performing QoS testing, which includes delay and jitter.

It's important to note that while these prior art references teach various aspects of network delay and jitter measurement, the specific combination of features in US7864816, such as an integrated circuit with a packet generator directly within the port's MAC and a controller designed to explicitly calculate delay that includes queue delay that occurs when the first packet is queued for transmission, and doing so at wirespeed to offload the CPU, would be the points of novelty that differentiate US7864816's claims from these prior art references. A full anticipation analysis would scrutinize whether each and every element of a US7864816 claim is found in a single prior art reference, or if the combination would be obvious over multiple references (obviousness under 35 U.S.C. § 103).