Obviousness

Obviousness Analysis under 35 U.S.C. § 103

A patent claim is unpatentable if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art (PHOSITA) to which the claimed invention pertains. The PHOSITA is a hypothetical person, not a genius or an inventor, who possesses ordinary skill, ordinary creativity, and ordinary knowledge in the relevant technical field at the relevant time, and is expected to follow conventional wisdom and apply known techniques in a predictable manner. To demonstrate obviousness, there must be a motivation to combine prior art teachings to arrive at the claimed invention with a reasonable expectation of success. This motivation can exist when references address the same problem and one reference provides a known technique that would suitably address that problem.

The patent US7826350 is directed to an intelligent network adaptor with an adaptive direct data placement scheme, aiming to improve receive data communication efficiency by selectively placing application data directly into application memory and moderating notification rates.

Person Having Ordinary Skill in the Art (PHOSITA)

In the context of US7826350, a PHOSITA would likely be a computer engineer or software developer with experience in network interface card (NIC) design, operating system network stacks, and high-performance data communication. This individual would be familiar with concepts such as TCP/IP offload engines (TOE), direct memory access (DMA), memory management, and various buffering strategies employed in network communication. They would also be aware of the challenges associated with high packet arrival rates, host processor overhead, and data copying latency in high-speed networks, as explicitly stated in the patent's background.

Potential Prior Art Combinations and Motivations

While a comprehensive prior art search is outside the scope of this analysis, based on the patent's own cited prior art and the general state of the art as described, several combinations could lead to an obviousness challenge. The patent itself mentions that "direct data placement (DDP) is known" and "it is now common for network adaptors to implement intelligence for the support of host processing, including to partly or completely offload protocol processing. Such adaptors are sometimes referred to as intelligent network adaptors." This suggests that the individual elements of "intelligent network adaptor" and "direct data placement" were known in the art.

The core innovative aspect of US7826350 lies in the adaptive nature of the direct data placement scheme and the selective provision of application memory information to the intelligent network adaptor (Claim 1), coupled with potential initial copying of data to an OS-associated buffer before direct placement into application memory (Claim 2, 5, 16). The patent also highlights the moderation of notification rates.

Here are potential combinations of prior art and motivations to combine, assuming relevant prior art exists disclosing the individual elements:

Combination 1: Intelligent Network Adaptor + Direct Data Placement (DDP) + Adaptive Buffer Management (e.g., based on buffer size)

• Hypothetical Prior Art 1: A patent or publication disclosing an "intelligent network adaptor" capable of offloading protocol processing (e.g., a TCP Offload Engine or TOE) and generally supporting Direct Data Placement (DDP) to host memory. For instance, US6226680B1 (Alacritech, Inc., "Intelligent network interface system method for protocol processing") and US6434620B1 (Alacritech, Inc., "TCP/IP offload network interface device") are cited references that broadly relate to intelligent network interfaces and TCP/IP offload. While not explicitly detailed in the provided text, it's reasonable to assume these or similar documents would teach the basic concept of an intelligent NIC performing DDP.
• Hypothetical Prior Art 2: A patent or publication disclosing methods for managing host memory buffers for network data, recognizing the overhead associated with data copying versus zero-copy mechanisms, and potentially discussing criteria for choosing between them, such as buffer size. This could come from a general operating system or network driver optimization technique.
• Motivation to Combine: A PHOSITA would be motivated to combine an intelligent network adaptor with DDP capabilities (Prior Art 1) with buffer management strategies (Prior Art 2) to optimize data transfer efficiency. The patent itself identifies the challenge of "memory bandwidth resources to copy application payload data from the operating system buffers to application buffers" and the "tradeoff between the cost of copying packet payload... and overhead cost associated with mapping an application buffer into a chain of memory descriptors (for zero copy)." This explicitly states the problem and the motivation to find an optimal solution. The idea of making an "adaptive copy vs. zero-copy decision... depending on various criteria" (as described in the patent) would be a logical step for a PHOSITA seeking to improve overall performance and reduce host burden. Specifically, using the size of the application buffer as a criterion for this adaptive decision (as claimed in Claim 1) is presented in the patent as a solution to this known tradeoff. If Prior Art 2 teaches this tradeoff and potential criteria, combining it with Prior Art 1 would be obvious.

Combination 2: Intelligent Network Adaptor + DDP + Initial Copy to OS Buffer + Subsequent Direct Placement

• Hypothetical Prior Art 1: As above, an intelligent network adaptor with DDP capabilities.
• Hypothetical Prior Art 2: A patent or publication addressing the scenario where an application may not have a receive buffer posted when data arrives, suggesting temporary storage in adaptor memory or an operating system buffer. The patent explicitly states, "Data that arrives during the time the application has no receive request in place may be saved in some memory—either in memory of the intelligent network adaptor or in host memory (e.g., in memory controlled by the operating system)."
• Motivation to Combine: A PHOSITA, faced with the problem of optimizing data delivery when application buffers are not immediately available (e.g., in synchronous I/O scenarios), would be motivated to combine the DDP capabilities of an intelligent NIC (Prior Art 1) with a strategy for handling temporarily un-posted application buffers (Prior Art 2). The patent describes this as using an operating system buffer "to save the received data" and then copying it to the application buffer when available, while subsequent data for the same request can be directly placed by the adaptor at an offset. This "adaptive copy avoidance" scheme addresses the latency of data transfer while enabling eventual zero-copy for later portions of the data. This combination would be obvious to a PHOSITA looking to minimize idle times and delays and reduce the likelihood of dropping packets, especially in the absence of continuous application buffer availability. The concept of performing the initial copy in parallel with setting up zero-copy for subsequent data (as described in the patent) further reinforces the motivation to improve efficiency.

Combination 3: Intelligent Network Adaptor + Moderated Notification Rate + Application-Level Signaling

• Hypothetical Prior Art 1: An intelligent network adaptor offloading protocol processing and capable of sending notifications to the host.
• Hypothetical Prior Art 2: A patent or publication discussing methods for moderating interrupt rates or host notifications in high-speed network environments, perhaps mentioning batching notifications or using timers. The patent notes that "Interrupt rate moderation schemes are known, but have limited effectiveness."
• Hypothetical Prior Art 3: A patent or publication discussing the interpretation of transport layer (e.g., TCP) control flags (FIN, URG, PSH) or application-level information for signaling important events. The patent explicitly describes how TCP flags "may loosely be considered application level signaling."
• Motivation to Combine: A PHOSITA would be motivated to combine an intelligent network adaptor (Prior Art 1) with known notification moderation techniques (Prior Art 2) to reduce host processing load. To ensure that reducing notifications does not negatively impact application latency or awareness of critical events, a PHOSITA would also incorporate the use of application-level signaling or transport-layer flags (Prior Art 3) to trigger "useful notifications" (as described in the patent). The patent clearly outlines the motivation: "an intelligent reduction in notification rate regarding data received from the network... may improve host system performance without affecting (or with minimal effect on) communication latency." Triggering notifications based on specific TCP flags (FIN, URG, PSH) or when a buffer is full, or a timer elapses (as described in the patent), directly addresses this motivation.

Consideration of Secondary Considerations:
The patent does not provide information regarding secondary considerations of non-obviousness such as commercial success, long-felt need, unexpected results, or industry acquiescence. In the absence of such information, the analysis primarily relies on the content of the prior art and the motivation of a PHOSITA to combine them.

It is important to note that without the specific content of the cited prior art references (or other relevant prior art), these are illustrative combinations. A definitive obviousness determination would require a thorough review of the actual disclosures of the identified prior art.