Prior art

Here is an analysis of the most relevant prior art for US Patent 7,702,742, based on the patent's own citations:

1. US5572688A

• Full Citation: US5572688A, Chen et al., "Method and apparatus for efficient communication in a data processing system"
• Publication/Filing Date: Published: November 5, 1996; Filed: October 28, 1994.
• Brief Description: This patent describes a communication system for efficient data transfer between processing nodes in a multiprocessing environment, utilizing a coherent communication adapter to handle memory access requests and maintain cache coherence. It involves request and response queues and a snooping mechanism.
• Potential Anticipation under 35 U.S.C. § 102: While it addresses inter-node memory access and data transfer, it does not explicitly disclose operating over a "lossy" network, assigning network sending priorities based on processor bus protocol transaction types, or the specific retransmission strategy (resending a timed-out packet and all subsequent packets of the same priority) employed by US7702742 to ensure ordered delivery across an unreliable network. Therefore, it does not appear to anticipate all elements of independent claims 1, 11, or 19.

2. US6058448A

• Full Citation: US6058448A, Dobbins et al., "Scalable coherent interface (SCI) using dynamic address translation"
• Publication/Filing Date: Published: May 2, 2000; Filed: October 22, 1997.
• Brief Description: This patent describes a system for a Scalable Coherent Interface (SCI) that allows multiple processors to share memory using dynamic address translation. It enables remote memory access by mapping remote memory addresses into a local address space and uses SCI packets for requests and responses, focusing on coherence and scalability.
• Potential Anticipation under 35 U.S.C. § 102: This patent relies on the SCI, a proprietary network known for its inherent reliability and ordered delivery. It does not address the challenges of a "lossy" network or the specific mechanisms in US7702742 for prioritizing network packets based on processor bus protocol transaction types and implementing a retransmission scheme to overcome packet loss and reordering in such a network. Thus, it does not anticipate the core inventive aspects of US7702742 related to lossy network handling.

3. US6243763B1

• Full Citation: US6243763B1, Arimilli et al., "Asynchronous packet passing for memory access operations"
• Publication/Filing Date: Published: June 5, 2001; Filed: September 30, 1999.
• Brief Description: This patent describes a data processing system that performs memory access operations using asynchronous packet passing, assigning sequence numbers to packets to ensure correct ordering of load and store operations even with multiple outstanding requests.
• Potential Anticipation under 35 U.S.C. § 102: While it addresses packet ordering and uses sequence numbers for memory access, it does not explicitly disclose operating over a "lossy" network with the specific retransmission logic of US7702742. Crucially, it lacks the teaching of assigning different sending priorities to network packets based on processor bus protocol transaction types (e.g., posted, non-posted, response) and transmitting them according to these priorities across an unreliable network. Therefore, it is unlikely to anticipate all elements of independent claims 1, 11, or 19.

4. US6460114B1

• Full Citation: US6460114B1, Gibson et al., "Coherent memory over a network"
• Publication/Filing Date: Published: October 8, 2002; Filed: June 27, 2000.
• Brief Description: This patent describes a system and method for supporting coherent memory operations across a network, involving a network interface that intercepts memory requests and directs them to local or remote memory, while maintaining data consistency.
• Potential Anticipation under 35 U.S.C. § 102: This patent focuses on cache coherence for memory accessed over a network. However, its abstract and general description do not indicate that it specifically addresses the challenges of a "lossy" network, such as dropped packets and reordering. It also does not disclose assigning network sending priorities based on processor bus protocol transaction types or the specific retransmission strategy to ensure reliable, in-order delivery over an unreliable network as taught by US7702742.

5. US6505260B1

• Full Citation: US6505260B1, Blumrich et al., "Method and apparatus for enabling processor to memory and memory to memory communications in a data processing system having a scalable coherent interface"
• Publication/Filing Date: Published: January 7, 2003; Filed: September 29, 2000.
• Brief Description: This patent describes enabling processor-to-memory and memory-to-memory communications in a data processing system using a Scalable Coherent Interface (SCI) network, allowing nodes to efficiently access remote memory.
• Potential Anticipation under 35 U.S.C. § 102: Similar to US6058448A, this patent operates within the context of an SCI network, which is inherently reliable and ordered. It does not teach the specific mechanisms required to ensure reliable and ordered memory transactions over a "lossy" network, including the prioritization of network packets based on processor bus protocol transaction types or the retransmission scheme described in US7702742.

6. US6745269B1

• Full Citation: US6745269B1, Hughes et al., "System and method for providing direct access to a memory of a remote device via a network"
• Publication/Filing Date: Published: June 1, 2004; Filed: October 19, 2001.
• Brief Description: This patent describes a system and method for direct access to remote memory via a network, where a network interface translates local memory requests into network packets for transparent and efficient remote memory access, potentially using RDMA.
• Potential Anticipation under 35 U.S.C. § 102: While it discusses remote memory access, the patent does not explicitly detail solutions for a "lossy network" or the specific prioritization scheme for network packets based on processor bus protocol transaction types. The retransmission strategy of US7702742, particularly resending all subsequent packets of the same priority, is also not evident. Thus, it lacks key inventive elements of US7702742.

7. US6792476B1

• Full Citation: US6792476B1, Dobbins et al., "Network fabric interconnect with memory mapping"
• Publication/Filing Date: Published: September 14, 2004; Filed: June 15, 2001.
• Brief Description: This patent describes a network fabric interconnect for coupling processing units, enabling memory mapping, address translation, and communication between processors and memory controllers for high-performance distributed computing.
• Potential Anticipation under 35 U.S.C. § 102: This patent generally describes a network interconnect with memory mapping, but its abstract does not provide details on addressing the issues of a "lossy network" or the specific prioritization and retransmission mechanisms of US7702742. It focuses on a "network fabric interconnect," typically implying a reliable and controlled environment, rather than a general-purpose lossy network.

8. US6854002B1

• Full Citation: US6854002B1, Blumrich et al., "Low latency memory-to-memory communication system for data processing networks"
• Publication/Filing Date: Published: February 8, 2005; Filed: October 11, 2001.
• Brief Description: This patent describes a low-latency memory-to-memory communication system for data processing networks, particularly optimized for use with a Scalable Coherent Interface (SCI), focusing on minimizing latency for remote memory accesses.
• Potential Anticipation under 35 U.S.C. § 102: Like other SCI-based references, this patent operates within a framework of inherent network reliability. It does not address the problem of reliable and ordered communication over a "lossy network" using the specific MTM transaction-type-based prioritization and retransmission scheme disclosed in US7702742.

9. US6910086B2

• Full Citation: US6910086B2, Gaskins et al., "Memory controller having a network interface unit"
• Publication/Filing Date: Published: June 21, 2005; Filed: June 21, 2002.
• Brief Description: This patent describes a memory controller that integrates a network interface unit (NIU), allowing it to function as a network endpoint and handle memory access requests from both local processors and remote devices over a network.
• Potential Anticipation under 35 U.S.C. § 102: This patent describes a system component (memory controller with integrated network interface) relevant to remote memory access. However, its abstract does not detail how it specifically addresses the challenges of a "lossy network," including the prioritization of network packets based on processor bus protocol transaction types or the specific retransmission logic of US7702742 to ensure reliable, ordered delivery.

10. US20020059483A1

• Full Citation: US20020059483A1, Gibson et al., "Network-to-memory transaction system and method"
• Publication/Filing Date: Published: May 16, 2002; Filed: October 17, 2001.
• Brief Description: This patent application describes a network-to-memory transaction system where a network interface unit processes memory requests originating from a network and directs them to local memory.
• Potential Anticipation under 35 U.S.C. § 102: This application describes the receiving end of network-based memory transactions. It does not, however, describe the sending-side mechanisms of US7702742 for handling a "lossy network," particularly the assignment of network sending priorities based on processor bus protocol transaction types and the retransmission strategy for ensuring ordered delivery across such a network.

11. US20030046429A1

• Full Citation: US20030046429A1, Hughes et al., "System and method for transparent remote memory access"
• Publication/Filing Date: Published: March 6, 2003; Filed: October 19, 2001.
• Brief Description: This patent application describes a system and method for transparent remote memory access, allowing a local device to access remote memory as if it were local, via a network interface that translates requests into network packets.
• Potential Anticipation under 35 U.S.C. § 102: This application focuses on transparent remote memory access. Similar to its granted counterpart (US6745269B1), it does not detail solutions for a "lossy network," prioritized packet transmission based on processor bus protocol transaction types, or the specific retransmission mechanism of US7702742 for guaranteed in-order delivery over an unreliable network.

12. US20040054796A1

• Full Citation: US20040054796A1, Blumrich et al., "Mechanisms for implementing a shared memory over a switched network"
• Publication/Filing Date: Published: March 18, 2004; Filed: September 17, 2002.
• Brief Description: This patent application describes mechanisms for implementing shared memory over a switched network (e.g., InfiniBand), including address translation and managing coherence and synchronization, using transaction identifiers and queues.
• Potential Anticipation under 35 U.S.C. § 102: This application discusses shared memory over a switched network, typically assumed to be reliable. While it deals with ordering using transaction identifiers and queues, it does not explicitly teach addressing a "lossy network" or the unique combination of assigning network sending priorities based on processor bus protocol transaction types, ordering transmission based on these priorities, and implementing the specific retransmission strategy (resending timed-out packets and all subsequent packets of the same priority) to overcome the challenges of a lossy network, as claimed in US7702742.

13. US20040078519A1

• Full Citation: US20040078519A1, Blumrich et al., "Network interface supporting virtualized direct memory access"
• Publication/Filing Date: Published: April 22, 2004; Filed: October 18, 2002.
• Brief Description: This patent application describes a network interface that supports virtualized direct memory access (DMA), enabling applications to directly access remote memory with improved performance, involving address translation and access rights management over a network.
• Potential Anticipation under 35 U.S.C. § 102: This application focuses on virtualized DMA for remote memory access. Its abstract does not describe mechanisms for addressing the specific problems of a "lossy network," such as prioritizing network packets based on processor bus protocol transaction types or the specific retransmission scheme to ensure reliable, in-order delivery over an unreliable network, which are central to US7702742.

14. US20050015509A1

• Full Citation: US20050015509A1, Gaskins et al., "Multi-port memory hub with direct attached network interface"
• Publication/Filing Date: Published: January 20, 2005; Filed: June 21, 2002.
• Brief Description: This patent application describes a multi-port memory hub with a direct-attached network interface, acting as an interface between processors, memory, and a network to enable efficient remote memory access.
• Potential Anticipation under 35 U.S.C. § 102: This application describes a hardware architecture for remote memory access. While providing a relevant system component, its abstract does not detail the methodological innovations of US7702742 for handling a "lossy network," including the specific prioritization of network packets based on processor bus protocol transaction types and the retransmission strategy for guaranteeing ordered delivery.

15. US20050060431A1

• Full Citation: US20050060431A1, Arimilli et al., "High performance architecture for a multi-node, single-system-image computer system"
• Publication/Filing Date: Published: March 17, 2005; Filed: September 15, 2003.
• Brief Description: This patent application describes a high-performance architecture for a multi-node, single-system-image computer system, detailing techniques for efficient inter-node communication and memory access to present multiple nodes as a single system.
• Potential Anticipation under 35 U.S.C. § 102: This application describes a high-level architecture for multi-node systems. However, its abstract does not specify the mechanisms for addressing a "lossy network" or the inventive priority-based transmission and retransmission scheme of US7702742 for memory transaction messages (MTMs). The focus is on overall system efficiency rather than the specific problem of reliable, ordered communication of processor bus protocol transactions across a lossy network.