Obviousness

US Patent 7636146 relates to an electro-optical panel, an electro-optical apparatus, and an electronic system, specifically addressing challenges in reliably connecting input terminals, particularly when dealing with varying signal characteristics and limited space. The patent's core invention revolves around differentiating the size and arrangement of input terminals based on the frequency components of the signals they carry and the characteristics of the connection method.

An obviousness analysis under 35 U.S.C. § 103 requires identifying prior art combinations that would render the claimed invention obvious to a person having ordinary skill in the art (PHOSITA), along with a motivation to combine those references. Based on the patent's own "Background Art" and "Summary" sections, several aspects of the claimed invention appear to be logical applications of known engineering principles to solve acknowledged problems in the field.

Common Elements in the Prior Art:
The patent explicitly states that a "known electro-optical apparatus" includes pixel electrodes, switching elements (TFTs), an opposing substrate with opposing electrodes, and a liquid crystal as an electro-optical material, arranged in a matrix. It also identifies as prior art "techniques which connect an input terminal formed on the electro-optical panel and a flexible substrate as a connection cable through an anisotropic conductive film", specifically citing Japanese Patent No. 2822558B2. This establishes that the basic structure of an electro-optical panel with input terminals connected via an anisotropic conductive film (ACF) on a flexible substrate is known in the art. Furthermore, the existence of scanning-line drive circuits, data-line drive circuits, and the supply of power, driving signals, and image signals to the panel are described as known in the background.

The patent itself identifies the problem addressed by the invention: "the resistance of an input terminal becomes smaller as the area thereof becomes larger. Thus, in terms of the reduction of the resistance value, it is desirable that the size of the input terminal is large. However, if the area of the input terminal is made large in terms of the reduction of the contact resistance, there has been a problem in that all of the input terminals cannot be disposed in a limited area.". Conversely, "when the area of the input terminal is made small in terms of the reduction of the mounting area, the contact resistance increases, and there has been a problem in that the driving signal cannot be input at a proper timing.".

Combinations of Prior Art and Motivation for Obviousness:

1. Combination: A known electro-optical panel (e.g., as generally described in the background of US7636146 and connected using methods like JP2822558B2) combined with terminals of varying areas, where the clock signal input terminal has a larger area than the image signal input terminal.

   • Motivation: The patent itself provides the motivation. A PHOSITA would recognize the existing trade-off between large terminal area for low resistance and small terminal area for high density. The patent also notes that driving signals (including clock signals) are critical for proper timing and that increased contact resistance due to small terminals can lead to improper timing. It is a known electrical engineering principle that higher frequency signals (like clock signals for scanning lines, which often have higher frequency components than image signals) are more susceptible to degradation (e.g., "dulling") due due to resistance and parasitic capacitance. To overcome the acknowledged problem of "improper timing" for driving signals and the known issue of signal dulling, a PHOSITA would be motivated to assign a larger area to the clock signal input terminal to reduce its contact resistance and improve signal integrity, while using smaller terminals for image signals (which have relatively low-frequency components and can tolerate a larger time constant) to save space and enable more terminals to be disposed in a limited area. This directly addresses the problems outlined in the patent's background.

2. Combination: The electro-optical panel of Combination 1, further including a power source terminal with an area not smaller than that of the clock signal input terminal.

   • Motivation: The patent states, "the resistance of the power source terminal should be kept as small as possible, because a predetermined voltage cannot be obtained by a voltage trap when the resistance is high.". This highlights a fundamental electrical engineering principle: power supply lines require low resistance to ensure stable voltage delivery and prevent voltage drops. If high-frequency clock signals require larger terminal areas to reduce resistance, a PHOSITA would logically apply the same or even more aggressive sizing (larger area) to power terminals, recognizing the critical need for stable and reliable power supply to the entire circuit, especially in an environment where resistance is a known concern.

3. Combination: The electro-optical panel of Combination 1 or 2, with image signal input terminals disposed in the central part of the substrate and clock signal (and power) input terminals disposed at the outer side of the substrate.

   • Motivation: The patent discloses a specific physical phenomenon related to the connection method: "When connecting each terminal with ACF, heat and pressure are applied, and thus the outer side of ACF tends to have a larger extension rate than the central part.". To prevent connection failures due to "slight misalignment of the connection" caused by these differential extension rates, the patent suggests that "disposing an input terminal having a wider area at a more outer side than the input terminal having a smaller area, it is possible to prevent a connection failure". A PHOSITA, aware of the differential contraction/extension rates of ACF and having terminals of different sizes (as taught by Combination 1 or 2), would be motivated to place the larger, more tolerant terminals (e.g., clock and power terminals) in the areas more prone to misalignment (the outer edges) to enhance connection reliability.

4. Combination: The electro-optical panel of Combination 1, 2, or 3, where the pitch interval of adjacent clock signal input terminals is an integer multiple of the pitch interval of adjacent image signal input terminals.

   • Motivation: The patent states that this arrangement simplifies "the estimation of the contraction rate of the mounting members... thereby it is possible to prevent a mounting failure in advance.". When designing flexible substrates for connection to terminal groups with mixed widths (as established in previous combinations), a PHOSITA would be motivated to simplify manufacturing and improve mounting reliability. Setting pitch intervals as integer multiples of a reference pitch is a common design practice in electrical and mechanical engineering to facilitate alignment, reduce manufacturing complexity, and improve accuracy, particularly when components of varying sizes are being connected on a common platform susceptible to dimensional changes (e.g., thermal contraction during ACF bonding). This would be an obvious choice for improving manufacturability and reducing defects.

In summary, the claims of US7636146 appear to represent an obvious combination of known prior art elements and general engineering principles to solve problems explicitly identified in the patent's background. The motivations for these combinations are either explicitly stated or are logical extensions of known characteristics and desired outcomes in electro-optical device design and manufacturing.