Obviousness

Obviousness Analysis of US Patent 7,629,634 under 35 U.S.C. § 103

This section analyzes the obviousness of US Patent 7,629,634, focusing on combinations of prior art references that would render the claims obvious to a person having ordinary skill in the art (POSITA), along with the motivation to combine them. The key inventive feature of US 7,629,634, as highlighted in the abstract and claims, is the presence of a "lateral contact layer" at the sidewalls of the source contact trenches. This aims to improve ohmic contact and ruggedness during UIS tests by reducing parasitic bipolar turn-on.

Prior Art References Identified in US 7,629,634

The patent itself references US 6,888,196 B2 (Nec Electronics Corporation) as a conventional vertical MOSFET, noting that prior art typically only has a P+-type region at the source contact trench bottom, lacking ohmic contact on the sidewalls.

Additional prior art that discusses trench MOSFET structures and their manufacturing include:

• US 2010/0127323 A1 (Force Mos Technology Co. Ltd.): This application, filed by the same assignee, discusses prior art MOSFET structures, including an N+ substrate, N-doped epitaxial layer, trench gates, P-body regions, and N+ source regions. It highlights the need for lower spreading resistance, smaller size, and reduced fabricating cost in trench MOSFETs. While this is a later publication than US7629634, it describes existing trench MOSFET structures that would have been known to a POSITA at the time of US7629634's filing.
• US 2004/0021173 A1 (American Philips Corporation): This patent application describes a MOSFET with a gate trench and a source trench, where the source trench is laterally spaced from the gate trench. It also describes a metal layer along the top surface contacting source regions, conductive material in source trenches, and body regions through P+ regions.
• US 7,629,646 B2 (Fwu-Iuan Hshieh / Force Mos Technology Co. Ltd.): This patent, also by an inventor and assignee related to US 7,629,634, describes a trench MOSFET with an epitaxial layer, trenches, oxide layers, P-type doping regions (P-body), N+ doping regions (N+ source), and a P+ doping region at the bottom of the trench contact for ohmic contact to the P-body.

Obviousness Combinations

Combination 1: US 6,888,196 B2 in view of the general knowledge of improving ohmic contact in semiconductor devices.

• Rationale: US 6,888,196 B2, as acknowledged by US 7,629,634, depicts a conventional trenched MOSFET where the P+-type region is located only at the source contact trench bottom, leading to poor ruggedness due to a lack of ohmic contact on the sidewall. A POSITA would be aware that good ohmic contact is crucial for device performance and reliability. Techniques for improving ohmic contact in semiconductor devices, such as increasing doping concentration in contact regions or forming highly doped layers at contact interfaces, were well-known in the art. The motivation to apply such a known technique to the sidewalls of the source contact trench in a MOSFET structure like that of US 6,888,196 B2 would be to address the recognized problem of poor ruggedness and parasitic bipolar turn-on, as explicitly stated in US 7,629,634. Forming a lateral contact layer with a doping concentration sufficient to achieve ohmic contact, but not so high as to significantly affect threshold voltage, would be an obvious design choice for a POSITA seeking to improve the device's avalanche performance.

Combination 2: US 2004/0021173 A1 in view of the need for improved contact and reduced resistance in trench MOSFETs.

• Rationale: US 2004/0021173 A1 describes a MOSFET with both gate and source trenches, and a metal layer making contact with source regions, conductive material in source trenches, and body regions through P+ regions. While it doesn't explicitly detail a lateral contact layer for the sidewalls of the source trench, it demonstrates the concept of using highly doped regions (P+ regions) to ensure good contact with the body region within the vicinity of the source trench. A POSITA seeking to further optimize the contact between the source metal and the body region in a trench MOSFET, particularly to reduce base resistance (Rp) and improve avalanche capability as motivated by the problems described in US 7,629,634, would consider extending or modifying the existing highly doped contact regions. Given the general objective of reducing resistance in trench MOSFETs, as also discussed in US 2010/0127323 A1, it would be obvious to a POSITA to introduce a lateral doped layer along the sidewall of the source contact trench, similar to the P*-type lateral contact layer of US 7,629,634, to ensure more complete and robust ohmic contact with the metal plug.

Motivation to Combine:

The primary motivation for a POSITA to combine these elements would be to improve the ruggedness and avalanche capability of trenched MOSFETs by establishing robust ohmic contact between the source metal and the P-type base layer. The prior art, including the device depicted in FIG. 1 of US 7,629,634, clearly identifies the problem of poor ohmic contact at the sidewalls of the source contact trench due to low doping concentration of the P-base, leading to the undesirable turn-on of a parasitic N+/P/N bipolar transistor during UIS tests. This problem would drive a POSITA to explore methods to enhance the contact in this critical region.

Furthermore, the general trend in MOSFET development, as indicated by references like US 2010/0127323 A1, is towards achieving lower resistance and smaller device sizes. A lateral contact layer contributes to both these goals by ensuring a more effective current path and preventing device degradation. The knowledge of doping techniques for forming highly conductive regions in semiconductors, combined with the recognized shortcomings of prior art trenched MOSFETs, would lead a POSITA to implement a lateral contact layer as claimed in US 7,629,634.