Prior art

US patent 7624138, titled "Method and apparatus for efficient integer transform," describes a method and apparatus for performing integer transforms on content data efficiently, particularly using Single-Instruction-Multiple-Data (SIMD) operations. The core of the invention involves specific instructions: a multiply-add instruction that generates sums of product pairs from packed data, and a horizontal-add instruction that adds adjacent summed-product pairs. These instructions are applied to perform integer transforms, such as 4x4 or 8x8 approximations of Discrete Cosine Transforms (DCTs).

The following are the most relevant prior art patent citations for US7624138, along with their details and potential anticipation under 35 U.S.C. § 102:

Most Relevant Prior Art

1. US7085795B2

   • Full Citation: US7085795B2, "An Apparatus and Method for Efficient Filtering and Convolution of Content Data," invented by Eric Debes, William W. Macy, Jonathan J. Tyler (assignee: Intel Corp.). Issued August 1, 2006.
   • Publication/Filing Date: Filed October 29, 2001.
   • Brief Description: This patent describes a system and method for efficient filtering and convolution of content data using packed data. It introduces specialized instructions, including those for performing "horizontal-add" operations that sum adjacent data elements (e.g., bytes, words, doublewords) within a register or between registers. The patent explicitly mentions a horizontal-add instruction capable of adding two word values to produce a 16-bit result.
   • Potential Anticipation (35 U.S.C. § 102): US7085795B2, sharing the same inventors and assignee, directly anticipates the "horizontal-add instruction" aspect of US7624138. Specifically, claims 2, 8, 11, 19, 28, 35, 44, 51, and 58 of US7624138, which cover adding adjacent summed-product pairs using a horizontal-add instruction, are potentially anticipated by the teaching of similar horizontal addition on packed data elements. The use of 16-bit results from such operations, as detailed in claims 4, 5, and 9, is also described within US7085795B2.

2. US5794017A

   • Full Citation: US5794017A, "Processor and method for performing multiplication and addition operations on a plurality of data elements in parallel," invented by Alexander Peleg, Shinya Shimada, Robert P. Colwell (assignee: Intel Corp.). Issued August 11, 1998.
   • Publication/Filing Date: Filed March 29, 1996.
   • Brief Description: This patent discloses a processor and corresponding method for executing a single instruction that performs both multiplication and addition operations on multiple packed data elements in parallel. It describes instructions like PMADDWD (Packed Multiply and Add Word) where corresponding 16-bit words from two source operands are multiplied, and the 32-bit products are then summed in pairs to produce 32-bit results in a destination register.
   • Potential Anticipation (35 U.S.C. § 102): US5794017A directly anticipates the "multiply-add instruction" central to US7624138. Claims 1, 7, 10, 18, 27, 34, 43, 50, and 57 of US7624138, which define generating sums of product pairs in response to a multiply-add instruction, are potentially anticipated. The concept of multiplying packed data elements (e.g., words) and summing adjacent products is explicitly taught. While US7624138 emphasizes byte data elements producing 16-bit sums (claims 4, 9), the core functionality of a single SIMD instruction performing a combined multiply-add on packed data elements is present.

3. US5727147A

   • Full Citation: US5727147A, "Method and apparatus for operating on packed data," invented by Seshadri Dattatri, Karl M. Guttag, Alexander Peleg, Shinya Shimada, Roman Shvets (assignee: Intel Corp.). Issued March 10, 1998.
   • Publication/Filing Date: Filed August 31, 1995.
   • Brief Description: This patent describes a foundational SIMD architecture for operating on packed data. It details a processor capable of storing multiple data elements (e.g., bytes, words, doublewords) in a single register and executing a single instruction to perform parallel operations (e.g., addition, subtraction, multiplication) on these elements. This patent lays the groundwork for packed data instructions.
   • Potential Anticipation (35 U.S.C. § 102): This patent broadly anticipates the fundamental concept of using SIMD operations on packed data, which is a core underlying technology for US7624138. Specifically, the general idea of packed arithmetic operations and manipulation of different data element sizes (e.g., bytes, words) as referenced in claims 1, 4, 10, 14, 15, 18 and related claims in US7624138 is anticipated. While it describes separate packed multiply and packed add instructions rather than a single multiply-add instruction, the enabling technology for such combined operations is disclosed.

4. US6360312B1

   • Full Citation: US6360312B1, "Method and apparatus for performing horizontal operations on packed data," invented by William W. Macy, Eric Debes, Jonathan J. Tyler (assignee: Intel Corp.). Issued March 19, 2002.
   • Publication/Filing Date: Filed January 20, 2000.
   • Brief Description: This patent, also by some of the inventors of US7624138 and assigned to Intel, focuses on horizontal operations on packed data. It describes methods and apparatus for combining adjacent data elements within a packed data operand (e.g., summing or subtracting adjacent words) using specific instructions. This directly relates to the horizontal-add and horizontal-subtract functionalities.
   • Potential Anticipation (35 U.S.C. § 102): US6360312B1 specifically teaches the "horizontal-add" operation on packed data. Claims 2, 8, 11, 19, 28, 35, 44, 51, and 58 of US7624138, which describe adding adjacent summed-product pairs using a horizontal-add instruction, are potentially anticipated. The patent provides detailed descriptions of performing such operations on various packed data types, including words, which aligns with the 16-bit data element operations mentioned in claims 4, 5, and 9 of US7624138.

These prior art documents, particularly those from Intel with overlapping inventors, demonstrate that the underlying SIMD instructions for packed data, including multiply-add and horizontal-add operations, were known before the priority date of US7624138. The novelty of US7624138 likely resides in the specific application and sequence of these operations for efficient integer transforms approximating discrete cosine transforms, especially the specific data widths and saturation logic implemented for that purpose.