Patent 6968001

Prior art

Earlier patents, publications, and products that may anticipate or render the claims unpatentable.

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Prior art

Earlier patents, publications, and products that may anticipate or render the claims unpatentable.

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To identify the most relevant prior art for US patent 6968001, I will examine the "Citations" and "Family Cites Families" sections of the provided patent text, as these typically list the prior art considered during prosecution. The information regarding publication/filing date and a brief description is provided within the patent text itself. I will then cross-reference these against the independent claims to determine potential anticipation under 35 U.S.C. § 102.

Cited Prior Art for US Patent 6968001:

Here are the patent citations listed in US6968001, along with their relevant details and potential anticipation:

Patent Citations (Directly cited by US6968001):

  1. US5268930A

    • Full Citation: US5268930A (en)
    • Publication Date: 1993-12-07
    • Priority Date: 1991-12-19
    • Assignee: Novatel Communications Ltd.
    • Title: Decision feedback equalizer
    • Brief Description: This patent describes a decision feedback equalizer. Decision Feedback Equalizers (DFE) are a type of equalizer that uses previously detected symbols to help cancel intersymbol interference (ISI) from currently received symbols. This is relevant to the general field of equalization addressed by US6968001.
    • Potential Anticipation (35 U.S.C. § 102): US5268930A teaches a type of equalizer. While US6968001 focuses on virtual parallel equalizers and a method for selecting an optimal configuration, this reference could potentially anticipate the broad concept of using an equalizer, particularly if the claims of US6968001 are interpreted very broadly without the "virtual parallel" or "selection" features. However, it is unlikely to anticipate the specific method of training and selecting among multiple virtual configurations.
  2. US5666378A

    • Full Citation: US5666378A (en)
    • Publication Date: 1997-09-09
    • Priority Date: 1994-03-18
    • Assignee: Glenayre Electronics, Inc.
    • Title: High performance modem using pilot symbols for equalization and frame synchronization
    • Brief Description: This patent describes a high-performance modem that uses pilot symbols for equalization and frame synchronization. The use of pilot signals for training and performance measurement is explicitly mentioned in US6968001 (e.g., in independent claims 13 and 15, and in the detailed description regarding MSE/C/I estimation from pilot signals).
    • Potential Anticipation (35 U.S.C. § 102): This reference explicitly teaches the use of pilot symbols for equalization. This could potentially anticipate aspects of US6968001, particularly claims 13 and 15, which specifically mention training on a "received pilot signal" and determining a performance measure based on it. The novelty of US6968001 in this context would likely reside in the "virtual parallel" aspect and the comparison and selection of multiple configurations, rather than simply using pilot symbols for training a single equalizer.
  3. US5787118A

    • Full Citation: US5787118A (en)
    • Publication Date: 1998-07-28
    • Priority Date: 1993-09-10
    • Assignee: Mitsubishi Denki Kabushiki Kaisha
    • Title: Adaptive equalizer and adaptive diversity equalizer
    • Brief Description: This patent describes an adaptive equalizer and an adaptive diversity equalizer. Adaptive equalizers are a core component of US6968001, which deals with optimizing their configuration.
    • Potential Anticipation (35 U.S.C. § 102): Similar to US5268930A, this reference broadly teaches adaptive equalizers. It could anticipate the general concept of an adaptive equalizer but is unlikely to anticipate the specific method of creating "virtual parallel" configurations and selecting an optimal one based on performance parameters, as claimed in US6968001.
  4. EP0782305A2

    • Full Citation: EP0782305A2 (en)
    • Publication Date: 1997-07-02
    • Priority Date: 1995-12-27
    • Assignee: Matsushita Electric Industrial Co., Ltd.
    • Title: Bidirectional DFE
    • Brief Description: This patent describes a bidirectional DFE (Decision Feedback Equalizer).
    • Potential Anticipation (35 U.S.C. § 102): This patent's relevance is similar to US5268930A, focusing on a specific type of equalizer. It may anticipate the general use of equalizers but not the "virtual parallel" optimization method of US6968001.
  5. US6016379A

    • Full Citation: US6016379A (en)
    • Publication Date: 2000-01-18
    • Priority Date: 1997-08-05
    • Assignee: Alcatel
    • Title: Method and facility for equalizing an electric signal distorted due to interference in the optical domain
    • Brief Description: This patent describes a method and facility for equalizing an electric signal distorted due to interference in the optical domain.
    • Potential Anticipation (35 U.S.C. § 102): This patent describes equalization in a different domain (optical). While it addresses signal equalization, the context and specific mechanisms are likely different enough to not directly anticipate the claims of US6968001 in a wireless communication system with virtual parallel equalizers.
  6. US6735244B1

    • Full Citation: US6735244B1 (en)
    • Publication Date: 2004-05-11
    • Priority Date: 1999-08-30
    • Assignee: Fujitsu Limited
    • Title: Data transmission system and receiver unit thereof
    • Brief Description: This patent describes a data transmission system and a receiver unit thereof.
    • Potential Anticipation (35 U.S.C. § 102): This patent's description is too general to assess specific anticipation without further details on its equalization methods. If it details a receiver unit with an equalizer that selects configurations based on performance, it could be highly relevant. Given the publication date (2004) is after the filing date of US6968001 (2002), its priority date (1999) would be key for 35 U.S.C. § 102 analysis.
  7. US20020196844A1

    • Full Citation: US20020196844A1 (en)
    • Publication Date: 2002-12-26
    • Priority Date: 2001-05-04
    • Assignee: Caly Networks
    • Title: Adaptive equalizer system for short burst modems and link hopping radio networks
    • Brief Description: This patent describes an adaptive equalizer system for short burst modems and link hopping radio networks.
    • Potential Anticipation (35 U.S.C. § 102): The priority date (2001-05-04) is prior to US6968001's filing date (2002-08-21). This reference teaches an "adaptive equalizer system." If it includes mechanisms for adjusting equalizer parameters based on performance or selecting between different configurations in a way that aligns with the "virtual parallel" concept of US6968001, it could be a significant piece of prior art, particularly for independent claims 1, 11, 12, 13, and 15, which cover methods and apparatus for configuring, training, estimating performance, comparing, and selecting equalizer parameters.

Family Cites Families (Cited by other patents in the same family as US6968001):

  1. JPH03244220A

    • Full Citation: JPH03244220A (en)
    • Publication Date: 1991-10-31
    • Priority Date: 1990-02-22
    • Assignee: Toshiba Corp
    • Title: Automatic equalizer
    • Brief Description: This patent describes an automatic equalizer.
    • Potential Anticipation (35 U.S.C. § 102): This is a broad disclosure of an automatic equalizer. It is highly unlikely to anticipate the specific "virtual parallel" and selection methods of US6968001, which represent an advancement in optimizing such equalizers.
  2. JPH04252609A

    • Full Citation: JPH04252609A (en)
    • Publication Date: 1992-09-08
    • Priority Date: 1991-01-29
    • Assignee: Canon Inc
    • Title: automatic equalizer
    • Brief Description: This patent describes an automatic equalizer.
    • Potential Anticipation (35 U.S.C. § 102): Similar to JPH03244220A, this reference broadly teaches an automatic equalizer and is unlikely to anticipate the specific features of US6968001 related to virtual parallel equalizers and selection based on performance.
  3. JPH10163934A

    • Full Citation: JPH10163934A (en)
    • Publication Date: 1998-06-19
    • Priority Date: 1996-12-03
    • Assignee: Matsushita Electric Ind Co Ltd
    • Title: Receiver
    • Brief Description: This patent describes a receiver.
    • Potential Anticipation (35 U.S.C. § 102): The description is very general ("Receiver"). Without more specific details on the equalization within this receiver, it's impossible to determine its potential for anticipation.
  4. JP3168576B2

    • Full Citation: JP3168576B2 (en)
    • Publication Date: 2001-05-21
    • Priority Date: 1990-07-09
    • Assignee: ソニー株式会社
    • Title: Waveform equalization filter device
    • Brief Description: This patent describes a waveform equalization filter device.
    • Potential Anticipation (35 U.S.C. § 102): This patent's priority date (1990-07-09) makes it significantly older than US6968001. It describes a "waveform equalization filter device," which is a foundational component. It likely establishes the general concept of equalization but not the specific methods of virtual parallel equalizers and selection described in US6968001.
  5. US6373888B1

    • Full Citation: US6373888B1 (en)
    • Publication Date: 2002-04-16
    • Priority Date: 1998-10-09
    • Assignee: Telefonaktiebolaget Lm Ericsson (Publ)
    • Title: Estimated channel with variable number of taps
    • Brief Description: This patent describes an estimated channel with a variable number of taps. The concept of varying the number of equalizer taps to adjust performance is a central theme in US6968001, which discusses setting coefficients to zero to effectively change equalizer length.
    • Potential Anticipation (35 U.S.C. § 102): This is a highly relevant reference. Its priority date (1998-10-09) is prior to US6968001. The teaching of an "estimated channel with variable number of taps" directly addresses the problem of optimizing equalizer length, which is a core part of the "virtual parallel equalizers" concept in US6968001 (e.g., in the discussion of setting tap coefficients to zero to change effective length). Depending on the details of how the "variable number of taps" is managed and optimized in US6373888B1, it could potentially anticipate aspects of claims 1, 11, 12, 13, and 15, particularly concerning the determination of different equalizer configurations based on tap length and the selection of an optimal configuration.
  6. US6522683B1

    • Full Citation: US6522683B1 (en)
    • Publication Date: 2003-02-18
    • Priority Date: 2000-08-10
    • Assignee: Qualcomm, Incorporated
    • Title: Method and apparatus for adaptive linear equalization for walsh covered modulation
    • Brief Description: This patent describes a method and apparatus for adaptive linear equalization for Walsh covered modulation.
    • Potential Anticipation (35 U.S.C. § 102): This patent, also by Qualcomm, has a priority date (2000-08-10) prior to US6968001. It describes an "adaptive linear equalization" method. While it mentions equalization, the specific focus on "Walsh covered modulation" might differentiate it. However, if it teaches adapting or optimizing equalizer parameters by comparing different configurations or performance metrics, it could be relevant to the general inventive concept of US6968001, specifically related to claims 1, 11, 12, 13, and 15 regarding adaptive equalization and optimization.

Most Relevant Prior Art Summary:

Based on the titles and brief descriptions, US6373888B1 ("Estimated channel with variable number of taps") and US20020196844A1 ("Adaptive equalizer system for short burst modems and link hopping radio networks") appear to be the most relevant prior art.

  • US6373888B1 directly addresses the concept of a variable number of taps in an estimated channel, which is a key element of how US6968001 implements "virtual" equalizers by effectively changing their length. The details of its optimization method would be critical in assessing its anticipatory effect on US6968001's claims, particularly those relating to selecting an optimal configuration.

  • US20020196844A1 (with its 2001 priority date) is highly relevant as it describes an "adaptive equalizer system." The specifics of how this system adapts and whether it involves comparing different configurations or performance metrics for selection would determine its direct impact on claims 1, 11, 12, 13, and 15, which cover methods and apparatus for configuring, training, estimating performance, comparing, and selecting equalizer parameters.

US5666378A ("High performance modem using pilot symbols for equalization and frame synchronization") is also highly relevant, particularly to claims 13 and 15, due to its explicit teaching of using pilot symbols for equalization, a feature central to the training and performance measurement aspects of those claims in US6968001.

Generated 5/23/2026, 6:45:57 PM