Prior art — US Patent 12373366

To identify the most relevant prior art for US patent 12373366, I will first examine the patent itself to understand its claimed subject matter, then review the patents cited in its priority and related application chain.

US Patent 12373366B2 Details

Publication Number: US12373366B2
Title: Memory with on-module power management
Inventors: Chi-She Chen, Jeffrey C. Solomon, Scott H. Milton, Jayesh Bhakta
Current Assignee: Netlist Inc
Filing Date: 2022-01-24
Publication Date: 2025-07-29
Priority Date: 2007-06-01 (Claimed from U.S. Provisional Patent Application No. 60/941,586)
Abstract: "In certain embodiments, a memory module includes a printed circuit board (PCB) having an interface that couples it to a host system for provision of power, data, address and control signals. First, second, and third buck converters receive a pre-regulated input voltage and produce first, second and third regulated voltages. A converter circuit reduces the pre-regulated input voltage to provide a fourth regulated voltage. Synchronous dynamic random access memory (SDRAM) devices are coupled to one or more regulated voltages of the first, second, third and fourth regulated voltages, and a voltage monitor circuit monitors an input voltage and produces a signal in response to the input voltage having a voltage amplitude that is greater than a threshold voltage."

Based on the abstract and description, the patent US12373366B2 claims a memory module with significant on-module power management features (e.g., multiple buck converters, voltage monitoring) in addition to a hybrid volatile/non-volatile memory architecture and a controller/data manager for interaction with a host system and internal memory data transfer. Key aspects include the integration of power regulation and monitoring directly onto the memory module, particularly in the context of hybrid Flash-DRAM systems.

The claims of US12373366B2 were not provided in the authoritative patent text snippet. Therefore, the analysis of potential anticipation will be based on the general inventive concepts outlined in the abstract and detailed description of US12373366B2.

Analysis of Prior Art from US12373366B2's Priority Chain and Related Applications

The most relevant prior art for US12373366B2 will typically be its direct parent applications and issued patents in the same family, as these documents disclose earlier stages or foundational aspects of the same inventive subject matter.

First, I need to address the discrepancy regarding US Pat. No. 6,671,243. The provided text states it's from U.S. patent application Ser. No. 13/905,048, filed May 29, 2013, but US6671243B1 was issued in 2003. This is a clear conflict.

The search confirms that U.S. Patent 6,671,243 was granted on December 30, 2003, with an application filing date of May 17, 2002. This patent, titled "Control signal generation circuit and method for a digital data bus," is indeed too early to be a continuation of an application filed in 2013 (U.S. patent application Ser. No. 13/905,048). It appears there is an error in the "RELATED APPLICATIONS" section of the provided text for US12373366B2 regarding US Pat. No. 6,671,243. Given the explicit instruction to interpret alphanumeric IDs literally and prefer search results that contradict training data, I will consider US6671243B1 as distinct prior art, not a direct continuation of Ser. No. 13/905,048 for the purpose of this analysis, but a separate reference. I will not include US13/905,048 as resulting in 6,671,243.

Here are the most relevant issued prior art patents from the family chain of US12373366B2:

Most Relevant Prior Art for US12373366B2

The following patents are identified from the "PRIORITY CLAIM" and "RELATED APPLICATIONS" sections of US12373366B2 and are ordered generally from most recent to earliest filing date within the direct lineage.

1. U.S. Patent No. 11,232,054

Full Citation: U.S. Pat. No. 11,232,054, titled "FLASH-DRAM HYBRID MEMORY MODULE", issued February 1, 2022.
Publication/Filing Date: Filed May 24, 2021 (Application Ser. No. 17/328,019).
Brief Description: This patent describes a Flash-DRAM hybrid memory module, which is a direct parent of US12373366B2. It would cover the fundamental concepts of combining volatile (DRAM) and non-volatile (Flash) memory on a single module, including the on-module controller and data manager functions, as well as the transparent operation to the host system. Given its direct lineage and title, it is expected to describe the core hybrid memory architecture.
Potential Anticipation (35 U.S.C. § 102): This patent likely anticipates claims of US12373366B2 relating to the general architecture of a hybrid Flash-DRAM memory module, the on-module controller (CDC) and data manager (DMgr) for controlling data flow between the host, DRAM, and Flash, memory address translation/mapping, handling of standard DDR protocols, and methods for pre-fetching or copying data between volatile and non-volatile memory subsystems (as described in the "Overview" and "Description of Example Embodiments" of US12373366B2). However, it may not explicitly anticipate the specific on-module power management features detailed in US12373366B2's abstract, unless those features were also present in its own claims or description.

2. U.S. Patent No. 11,016,918

Full Citation: U.S. Pat. No. 11,016,918, titled "Flash-Dram Hybrid Memory", issued May 25, 2021.
Publication/Filing Date: Filed December 30, 2020 (Application Ser. No. 17/138,766).
Brief Description: Another direct parent patent, this also details a Flash-DRAM hybrid memory system. Its description would be highly relevant to the architecture, operation, and control mechanisms of such a module.
Potential Anticipation (35 U.S.C. § 102): Similar to US11232054, this patent is likely to anticipate claims related to the overall hybrid memory module structure, the functions of the on-module controller and data manager, and methods for managing data transfer and memory space configuration (e.g., presenting a unified memory space, application-specific partitioning, booting information copy, block management). It would establish the core inventive concept of a functional hybrid memory module.

3. U.S. Patent No. 9,928,186

Full Citation: U.S. Pat. No. 9,928,186, titled "Flash-Dram Hybrid Memory Module", issued March 27, 2018.
Publication/Filing Date: Filed August 31, 2015 (Application Ser. No. 14/840,865).
Brief Description: This patent, a continuation in the same family, describes a Flash-DRAM hybrid memory module. It would cover the core inventive features related to integrating both memory types and managing their operation on a single DIMM-like module.
Potential Anticipation (35 U.S.C. § 102): Anticipates claims related to the fundamental design of a hybrid memory module, including the presence of volatile and non-volatile memory subsystems, an on-module controller, and a data manager for orchestrating memory operations and data transfers between the host and the internal memory components. Many of the functional aspects of the controller and data manager are likely disclosed here.

4. U.S. Patent No. 9,158,684

Full Citation: U.S. Pat. No. 9,158,684, titled "Flash-Dram Hybrid Memory Module", issued October 6, 2015.
Publication/Filing Date: Filed September 17, 2014 (Application Ser. No. 14/489,269).
Brief Description: This patent is another continuation focused on Flash-DRAM hybrid memory modules, further establishing the core technology.
Potential Anticipation (35 U.S.C. § 102): Anticipates claims pertaining to the hybrid memory architecture, the concept of a memory module with an on-board controller and data manager for managing heterogeneous memory types, and the method of operating such a module to present a unified memory space or handle data transfers efficiently.

5. U.S. Patent No. 8,874,831

Full Citation: U.S. Pat. No. 8,874,831, titled "Flash-Dram Hybrid Memory Module", issued October 28, 2014.
Publication/Filing Date: Filed July 26, 2012 (Application Ser. No. 13/559,476).
Brief Description: This patent, a continuation of earlier applications, describes a Flash-DRAM hybrid memory module, continuing the evolution of the core invention.
Potential Anticipation (35 U.S.C. § 102): This patent is highly likely to anticipate the broader claims of US12373366B2 concerning the hybrid memory module, its volatile and non-volatile components, the on-module controller, and the data management functions, especially those related to data buffering, formatting, error correction, and independent/concurrent transfers between memory segments.

6. U.S. Patent No. 8,301,833

Full Citation: U.S. Pat. No. 8,301,833, titled "Non-Volatile Memory Module", issued October 30, 2012.
Publication/Filing Date: Filed September 29, 2008 (Application Ser. No. 12/240,916). This patent claims benefit of U.S. Provisional Patent Application No. 60/941,586, filed June 1, 2007, which is the earliest priority date for US12373366B2.
Brief Description: This patent describes a non-volatile memory module, which serves as a foundational patent in the family, introducing concepts of integrating non-volatile memory (e.g., Flash) into a DIMM form factor, potentially with some volatile buffering. It's a direct ancestor to the hybrid module concept.
Potential Anticipation (35 U.S.C. § 102): This patent is likely to anticipate claims regarding the basic concept of a memory module incorporating non-volatile memory and possibly a volatile buffer. It would lay the groundwork for the controller and data manager functionalities required for such a module, including the general methods for data transfer and management between memory types, even if not fully hybrid.

7. U.S. Patent No. 8,677,060

Full Citation: U.S. Pat. No. 8,677,060, titled "Isolation Switching For Backup Of Registered Memory", issued March 18, 2014.
Publication/Filing Date: Filed May 29, 2013 (Application Ser. No. 13/905,053).
Brief Description: This patent describes a memory system with isolation switching for backing up registered memory. This directly relates to the concept of managing memory states, particularly during power events or other trigger conditions, and ensuring data integrity between volatile and non-volatile storage. The mention of "backup" functionality is highly relevant.
Potential Anticipation (35 U.S.C. § 102): This patent is highly likely to anticipate claims of US12373366B2 related to backup and restore capabilities, particularly the use of a circuit (e.g., switch) to selectively isolate the controller from the volatile memory and couple the volatile memory to a host system in a first mode, and selectively couple the controller to the volatile memory for data transfer with non-volatile memory in a second mode. This directly addresses aspects of the "memory system" overview in US12373366B2.

8. U.S. Patent No. 8,516,187

Full Citation: U.S. Pat. No. 8,516,187, titled "Data Transfer Scheme For Non-Volatile Memory Module", issued August 20, 2013.
Publication/Filing Date: Filed June 28, 2012 (Application Ser. No. 13/536,173).
Brief Description: This patent focuses on data transfer schemes within a non-volatile memory module. This is directly relevant to the data manager's role in US12373366B2.
Potential Anticipation (35 U.S.C. § 102): Anticipates claims related to the data manager's functions in controlling data flow rate, transfer size, buffering, error correction, and overall data traffic between the memory controller, volatile memory, and non-volatile memory. This patent provides foundational elements for the data management aspects described in US12373366B2.

9. U.S. Patent No. 9,269,437

Full Citation: U.S. Pat. No. 9,269,437, titled "Flash-Dram Hybrid Memory Module", issued February 23, 2016.
Publication/Filing Date: Filed September 17, 2014 (Application Ser. No. 14/489,332).
Brief Description: This patent is another continuation of the hybrid memory module concept, indicating further development and refinement of the core technology.
Potential Anticipation (35 U.S.C. § 102): Similar to other "Flash-DRAM Hybrid Memory Module" patents, this would likely anticipate claims concerning the combined volatile and non-volatile memory, the on-module controller, and data manager, and the methods of integrating and operating these components on a memory module.

10. U.S. Patent No. 8,904,099

Full Citation: U.S. Pat. No. 8,904,099, titled "Isolation Switching For Backup Of Registered Memory", issued December 2, 2014.
Publication/Filing Date: Filed February 5, 2014 (Application Ser. No. 14/173,219).
Brief Description: This patent, a continuation of US8677060, further elaborates on isolation switching for memory backup. It directly addresses the backup/restore mechanism and the selective coupling/isolation of components.
Potential Anticipation (35 U.S.C. § 102): Highly likely to anticipate claims in US12373366B2 related to the selective isolation and coupling of the controller, volatile memory, and host system for backup and restore operations, including the first and second modes of operation as described in US12373366B2's overview section concerning a "memory system."

11. U.S. Patent No. 9,921,762

Full Citation: U.S. Pat. No. 9,921,762, titled "Memory module", issued March 20, 2018.
Publication/Filing Date: Filed September 17, 2014 (Application Ser. No. 14/489,281).
Brief Description: This patent generally describes a memory module, likely encompassing aspects of hybrid memory and its management given its position in the family chain.
Potential Anticipation (35 U.S.C. § 102): Depending on its specific claims, this patent could anticipate various architectural or functional claims of US12373366B2 related to the memory module itself, its components (volatile, non-volatile memory, controller), and their interaction.

12. U.S. Patent No. 8,904,098

Full Citation: U.S. Pat. No. 8,904,098, titled "Memory system with on-module power management", issued December 2, 2014.
Publication/Filing Date: Filed September 24, 2012 (Application Ser. No. 13/625,563).
Brief Description: Crucially, this patent explicitly has "Memory system with on-module power management" in its title, making it highly relevant to the core subject matter of US12373366B2. It claims the benefit of U.S. Provisional Application No. 61/583,775, filed Sep. 23, 2011. This suggests that the on-module power management aspect was developed and claimed much earlier in the family.
Potential Anticipation (35 U.S.C. § 102): This patent is most highly likely to anticipate the claims of US12373366B2 that relate to the specific "on-module power management" features, including the use of buck converters, voltage monitoring, and a secondary power supply (e.g., capacitor bank) and switching mechanisms for power transitions (as described in FIG. 16 and associated text of US12373366B2). Given the identical core concept in the title, it likely contains detailed disclosures and claims that are very similar or identical to the power management aspects of US12373366B2.

13. U.S. Patent No. 6,671,243

Full Citation: U.S. Pat. No. 6,671,243, titled "Control signal generation circuit and method for a digital data bus", issued December 30, 2003.
Publication/Filing Date: Filed May 17, 2002.
Brief Description: This patent describes a control signal generation circuit and method for a digital data bus. While generally related to memory bus control, its earlier date and specific title suggest it may not directly disclose the hybrid Flash-DRAM architecture with on-module controllers, data managers, or the specific on-module power management features of US12373366B2.
Potential Anticipation (35 U.S.C. § 102): Less likely to anticipate the core hybrid memory or on-module power management claims of US12373366B2, but could potentially anticipate very broad, generic claims relating to memory control signals or bus interface if such claims are present in US12373366B2. Given its age and general description, it's less direct prior art compared to the other family members.

In summary, the most relevant prior art documents are the issued patents in the direct priority chain, especially those explicitly titled "Flash-DRAM Hybrid Memory Module" or "Memory system with on-module power management," as these directly address the core inventive concepts of US12373366B2. U.S. Pat. No. 8,904,098 stands out as being particularly relevant to the "on-module power management" aspect of US12373366B2.