Patent 12373366

Obviousness

Combinations of prior art that suggest the claimed invention would have been obvious under 35 U.S.C. § 103.

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Obviousness

Combinations of prior art that suggest the claimed invention would have been obvious under 35 U.S.C. § 103.

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Obviousness Analysis of US Patent 12373366 under 35 U.S.C. § 103

This analysis considers US patent 12373366 ("Memory with on-module power management") and evaluates the obviousness of its claims based solely on the "Prior Art" section provided within the patent text. Since the explicit claims of US12373366 are not separately enumerated in the provided text, this analysis will infer the inventive concepts from the "Overview" section of US12373366, which typically summarizes the scope of the claims.

The core inventive concepts of US12373366, as summarized in its "Overview" section, include a memory module with a non-volatile memory subsystem (e.g., Flash), a volatile memory subsystem (e.g., DRAM), an on-module data manager, and an on-module controller. This controller is operable to receive commands from a host system's memory controller, direct the operation of both memory subsystems, and manage data transfer between them, often presenting a unified memory space to the host. The patent also describes various advanced data management techniques and on-module power management.

Identified Prior Art References:

The "Prior Art" section of US12373366 describes the following relevant systems:

  1. Conventional Memory Arrangement (FIG. 1): Illustrates data transfer bottlenecks due to the CPU controlling I/O for both SSD/HD and DRAM DIMMs. [cite: The "BACKGROUND" section, "FIG. 1 is a block diagram illustrating the path of data transfer, via a CPU, of a conventional memory arrangement"]
  2. EcoRAM™ Architecture (FIG. 2): A Flash-based SSD system in a DIMM form factor, using a small DRAM as a data buffer. It connects to the CPU via a high-speed interface (e.g., HyperTransport) but requires an "EcoRAM Accelerator™" which occupies a CPU socket, reducing server performance. It also exhibits a significant disparity between read and write throughput rates. [cite: "FIG. 2 is a block diagram of a known EcoRAMTM architecture", "The EcoRAMTM is populated with Flash memories and a relatively small memory capacity using DRAMs which serve as a data buffer.", "due to the interface protocol difference between DRAM and Flash, an interface device, EcoRAM AcceleratorTM), which occupies one of the server's CPU sockets is used"]
  3. Non-Volatile DIMM (NVDIMM) (FIGS. 3A, 3B): A memory system (300) comprising a non-volatile (Flash) memory subsystem (302) and a volatile (DRAM) memory subsystem (304). It includes an NVDIMM controller (306) that receives and interprets commands from the system memory controller hub (MCH) and controls both DRAM and Flash operations. An internal bus (308) is used for data transfer between the DRAM and Flash. NVDIMMs include a power subsystem (e.g., battery or capacitor) for energy storage to copy DRAM data into Flash upon power loss. [cite: "FIGS. 3 A and 3 B are block diagrams of a non-volatile memory DIMM or NVDIMM", "a memory system 300 includes a non-volatile (for example Flash) memory subsystem 302 and a volatile (for example DRAM) memory subsystem 304", "An NVDIMM controller 306 receives and interprets commands from the system memory controller hub (MCH). The NVDIMM controller 306 control the NVDIMM DRAM and Flash memory operations.", "an internal bus 308 is used for data transfer between the DRAM and Flash memory subsystems."]
  4. Flash-DRAM Hybrid DIMM (FDHDIMM) (FIGS. 4A, 4B):
    • FIG. 4A: Shows a general architecture where the FDHDIMM interfaces with an MCH and operates as a high-density DIMM. An FDHDIMM controller (404) controls the Flash memory (402). The DRAM (406) is primarily used as a data buffer, buffering data transferred from Flash to MCH at DRAM access speeds. The controller manages data transfer from DRAM to Flash. This architecture performs "pre-fetch read data operation from the Flash 402 to the DRAM 406" to hide Flash latency. The MCH recognizes the physical density as Flash alone. [cite: "FIG. 4 A a general architecture for a Flash and DRAM hybrid DIMM (FDHDIMM) system 400 is shown in FIG. 4 A", "the FDHDIMM interfaces with an MCH (memory controller hub) to operate and behave as a high density DIMM, wherein the MCH interfaces with the non-volatile memory subsystem (for example Flash) 402 is controlled by an FDHDIMM controller 404", "the volatile memory subsystem (for example DRAM) 406 is primarily used as a data buffer or a temporary storage location", "a read operation can be performed by the MCH by sending an activate command ... to conduct a pre-fetch read data operation from the Flash 402 to the DRAM 406", "the MCH recognizes the physical density of an FDHDIMM operating as a high density DIMM as the density of Flash alone"]
    • FIG. 4B: Describes an FDHDIMM operating as a DDR DIMM with SSD. The MCH can view it as a combination of DRAM DIMM and SSD (managing two address spaces) or as an on-DIMM Flash with SSD in an extended memory space behind the DRAM. Crucially, "all data movement occurs on the FDHDIMM," which provides better performance than moving data through the CPU. [cite: "An example of FDHDIMM operating as a DDR DIMM with SSD is shown in FIG. 4 B", "the MCH needs to manage two address spaces, one for the DRAMs 402 ′ and one for the Flash 404 ′", "the MCH views the FDHDIMM 400 ′ as an on-DIMM Flash with the SSD in an extended memory space that is behind the DRAM space", "Since all data movement occurs on the FDHDIMM, this mode will provide better performance than if the data were to be moved through or via the CPU."]

Obviousness Analysis: Combination of NVDIMM (FIGS. 3A, 3B) and FDHDIMM (FIGS. 4A, 4B)

A person having ordinary skill in the art (PHOSITA) would have been motivated to combine the teachings of the NVDIMM (FIGS. 3A, 3B) and the FDHDIMM (FIGS. 4A, 4B) to address known problems in computer memory systems, specifically the CPU I/O bottleneck (as highlighted in FIG. 1 of US12373366) and the performance disparity between volatile and non-volatile memory (as discussed in relation to EcoRAM™ in FIG. 2). The overarching motivation would be to create a more efficient, high-performance, and reliable hybrid memory module that operates transparently to the host system.

Rationale for Combination and How it Renders US12373366's Concepts Obvious:

  1. Memory Module with Volatile, Non-Volatile Memory, and an On-Module Controller:

    • NVDIMM (FIGS. 3A, 3B) explicitly teaches a memory module comprising both non-volatile (Flash 302) and volatile (DRAM 304) memory subsystems, along with an NVDIMM controller (306) that manages both. [cite: "a memory system 300 includes a non-volatile (for example Flash) memory subsystem 302 and a volatile (for example DRAM) memory subsystem 304", "An NVDIMM controller 306 receives and interprets commands from the system memory controller hub (MCH). The NVDIMM controller 306 control the NVDIMM DRAM and Flash memory operations."]
    • FDHDIMM (FIG. 4A) further reinforces this by showing a Flash and DRAM hybrid DIMM system with an FDHDIMM controller (404) that controls the Flash memory (402). [cite: "the non-volatile memory subsystem (for example Flash) 402 is controlled by an FDHDIMM controller 404"]
    • A PHOSITA would find it obvious to integrate these components onto a single memory module, managed by a common controller, as taught by both references.

  2. Volatile Memory Subsystem (DRAM) as a Buffer for Non-Volatile Memory (Flash):

    • EcoRAM™ (FIG. 2) clearly states that its DRAMs "serve as a data buffer" for Flash memories. [cite: "The EcoRAMTM is populated with Flash memories and a relatively small memory capacity using DRAMs which serve as a data buffer."]
    • FDHDIMM (FIG. 4A) states that the DRAM (406) "is primarily used as a data buffer or a temporary storage location" to buffer data between Flash (402) and the MCH. [cite: "the volatile memory subsystem (for example DRAM) 406 is primarily used as a data buffer or a temporary storage location"]
    • The utility of DRAM as a buffer for slower Flash memory to improve overall performance is well-established in the prior art. It would be obvious for a PHOSITA to incorporate this buffering strategy in a hybrid memory module.

  3. On-Module Data Manager / Data Transfer Fabric for Data Exchange Between Memory Subsystems:

    • NVDIMM (FIGS. 3A, 3B) discloses an "internal bus 308 is used for data transfer between the DRAM and Flash memory subsystems." [cite: "an internal bus 308 is used for data transfer between the DRAM and Flash memory subsystems."]
    • FDHDIMM (FIG. 4B) explicitly teaches that "all data movement occurs on the FDHDIMM" (between Flash and DRAM), leading to "better performance than if the data were to be moved through or via the CPU." [cite: "Since all data movement occurs on the FDHDIMM, this mode will provide better performance than if the data were to be moved through or via the CPU."]
    • Given the motivation to offload the CPU and improve on-module data transfer performance, a PHOSITA would find it obvious to implement a dedicated data management logic or "data transfer fabric" (as described in US12373366's overview) building upon the NVDIMM's internal bus and the FDHDIMM's emphasis on on-module data movement. The functions attributed to the data manager (e.g., control data flow rate, transfer size, error correction) are standard features expected in sophisticated memory controllers or data paths.

  4. Controller Directing Operations and Data Transfer Based on Host Commands and Protocols (e.g., DDR):

    • Both the NVDIMM controller (306) and the FDHDIMM controller (404) receive and interpret commands from the MCH to control their respective memory operations and data transfers. [cite: "An NVDIMM controller 306 receives and interprets commands from the system memory controller hub (MCH). The NVDIMM controller 306 control the NVDIMM DRAM and Flash memory operations.", "the FDHDIMM interfaces with an MCH (memory controller hub) to operate and behave as a high density DIMM, wherein the MCH interfaces with the non-volatile memory subsystem (for example Flash) 402 is controlled by an FDHDIMM controller 404"]
    • FDHDIMM (FIG. 4B) is described as "operating as a DDR DIMM." [cite: "An example of FDHDIMM operating as a DDR DIMM with SSD is shown in FIG. 4 B"] It is a common design goal for memory modules to adhere to industry standard protocols (like DDR, DDR2, DDR3, DDR4 mentioned in US12373366) for transparent operation with host systems. A PHOSITA would naturally design the controller to receive standard commands and direct internal operations accordingly.

  5. Pre-fetching Data from Non-Volatile to Volatile Memory:

    • FDHDIMM (FIG. 4A) explicitly teaches a "pre-fetch read data operation from the Flash 402 to the DRAM 406" initiated by an MCH command. [cite: "a read operation can be performed by the MCH by sending an activate command ... to conduct a pre-fetch read data operation from the Flash 402 to the DRAM 406"] This technique is directly taught in the prior art for performance enhancement.

  6. Presentation of a Unified Memory Space to the Host Controller:

    • FDHDIMM (FIG. 4A) states that "the MCH recognizes the physical density of an FDHDIMM operating as a high density DIMM as the density of Flash alone." [cite: "the MCH recognizes the physical density of an FDHDIMM operating as a high density DIMM as the density of Flash alone"] This demonstrates a prior art concept of abstracting the underlying hybrid memory configuration to simplify the host interface. A PHOSITA, motivated to further simplify interaction and achieve full transparency (especially given the criticism of EcoRAM requiring an accelerator), would find it obvious to extend this abstraction to a fully "unified memory space."

  7. On-Module Power Management for Backup:

    • NVDIMM (FIGS. 3A, 3B) explicitly includes a "power subsystem (not shown) that can include a battery or a capacitor as a means for energy storage to copy DRAM memory data into Flash memory when power loss occurs." [cite: "the examples of FIGS. 3 A and 3 B are directed to architectures of a non-volatile DIMM (NVDIMM) NVDIMM system that may use a power subsystem (not shown) that can include a battery or a capacitor as a means for energy storage to copy DRAM memory data into Flash memory when power loss occurs, is detected, or is anticipated to occur during operation"]
    • While specific voltage conversion elements (e.g., buck converters) are not detailed in the NVDIMM description, the need to manage power from such backup sources (batteries/capacitors) to ensure proper operation of memory elements and controllers during power down is a fundamental electrical engineering challenge. A PHOSITA would find it obvious to integrate known power management circuits (e.g., voltage regulators, monitors, and converters) to efficiently provide the necessary voltages and manage the backup process.

  8. Advanced Data Management (e.g., copying closed blocks, aborting if re-opened):

    • The use of DRAM as a buffer (EcoRAM, FDHDIMM 4A) inherently involves managing data writes from the buffer to the main non-volatile storage. The concept of a "closed block" (i.e., a data block in the buffer ready for write-back) is a standard aspect of cache and buffer management.
    • The NVDIMM's function of backing up DRAM data to Flash demonstrates the underlying mechanism. [cite: "copy DRAM memory data into Flash memory when power loss occurs"]
    • A PHOSITA would find it obvious to implement logic within the controller to manage the write-back of these "closed blocks" to Flash. Furthermore, ensuring data consistency by aborting a write-back and erasing the target Flash block if the corresponding DRAM block is re-opened (i.e., modified before write completion) is a common and logical refinement for data integrity in a buffered memory system.

Conclusion:

Based on the combination of NVDIMM (FIGS. 3A, 3B) and FDHDIMM (FIGS. 4A, 4B), a PHOSITA would have been motivated to develop a memory module with the characteristics described in the "Overview" of US12373366. The NVDIMM provides the foundational hybrid memory module with on-module control and power backup, while the FDHDIMM offers specific performance enhancements like DRAM buffering and pre-fetching, along with the critical teaching of performing data transfers between volatile and non-volatile memory entirely on the DIMM to bypass CPU bottlenecks. Many of the features of US12373366, such as the on-module controller and data manager, DRAM buffering, pre-fetching, unified memory space presentation, and on-module power management, are either explicitly taught or would be an obvious combination or refinement of the disclosed prior art elements for a PHOSITA seeking to improve hybrid memory system performance and transparency. Specific refinements like "slicing" for power savings (FIG. 21, 22 of US12373366) might represent further inventive steps; however, the core architecture and many of the described functionalities of US12373366 would be considered obvious when combining the NVDIMM and FDHDIMM prior art references.

Generated 5/26/2026, 12:47:08 PM