Obviousness

Obviousness Analysis under 35 U.S.C. § 103

A patent claim is obvious if "the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains." 35 U.S.C. § 103. This analysis considers the scope and content of the prior art, differences between the prior art and the claims, and the level of ordinary skill in the art, along with any secondary considerations of non-obviousness.

For US Patent 11886750, with a priority date of February 6, 2019, the relevant prior art includes published materials available before this date.

Claim 1

Claim 1 describes a method for executing data processing operations comprising:

1. Providing a compute node communicatively coupled to a host computer and operative to manage data processing operations independent of the host computer.
2. Providing a programmable logic component in the compute node configured to execute data processing operations in cooperation with a first memory component.
3. Providing a data mover component in the compute node configured to facilitate data communications between the programmable logic component and a second memory component.
4. Providing a set of instructions enabling the programmable logic component to reformat a block of data comprising original records (each with multiple field types) into new records (each with a single field type).
5. Utilizing a plurality of communications channels to transfer data associated with the reformatted data block between the programmable logic component and the first memory component.

A person having ordinary skill in the art (POSA) in the field of data processing and computer architecture would likely have been motivated to combine known elements to achieve the functionality of Claim 1.

Combination of Prior Art:

• Distributed Processing and Independent Compute Nodes: The concept of a "compute node" managing data processing operations independently of a host computer is well-established in distributed computing environments. CPC class G06F15/16 (Combinations of two or more digital computers for simultaneous processing of several programs) and G06F15/163 (Interprocessor communication) cover this widely. A POSA would be familiar with architectures where specialized nodes offload tasks from a host for performance or resource management.
• Programmable Logic Components (FPGAs) in Data Processing: The use of FPGAs for accelerating data processing is also a common practice. US11886750 itself identifies FPGAs (e.g., KintexTM KU095 FPGA, Xilinx ZynqTM Ultrascale+TM ZU9EG FPGA) as suitable for the programmable logic component (compute array 142 and router 122). A POSA would readily understand the benefits of FPGAs for custom data manipulation and high-throughput operations.
• Data Mover Components (DMAs): DMA controllers are fundamental to efficient data transfer within computer systems, especially between processing units and memory. The patent mentions DMAs 146a and 146b facilitating data communications. CPC class G06F3/0655 (Vertical data movement, i.e., input-output transfer; data movement between one or more hosts and one or more storage devices) and G06F3/0658 (Controller construction arrangements) encompass these aspects.
• Data Reformatting for Performance: The reformatting of data from record-centric to field-centric (columnar) is a known technique to optimize data access and processing for analytical queries. This columnar storage often improves cache utilization and reduces I/O when only a subset of fields is needed for an operation. Figures 10 and 11 of the patent explicitly illustrate this reformatting, and the specification notes that this increases performance for analytic algorithms.
• Multiple Communication Channels for Data Transfer: Utilizing multiple communication channels to transfer data between a programmable logic component and memory is a standard approach to enhance throughput and reduce bottlenecks. This is implicit in high-performance computing and storage systems, particularly those using parallel access memory or multi-channel interfaces. CPC class G06F3/0613 (Improving I/O performance in relation to throughput) directly addresses this.

Motivation for Combination:

A POSA would be motivated to combine these elements to improve the efficiency and performance of data analytics. The problem of processing large datasets with complex analytical algorithms and minimizing processor/network wait states is a long-standing challenge addressed by these individual components.

• Synergy for Performance: The combination of a specialized compute node with a programmable logic component (FPGA) and efficient data movers (DMAs) is a natural progression for offloading and accelerating data-intensive tasks from a host.
• Optimization through Data Reformatting: Reformatting data into a columnar structure before processing on an FPGA further optimizes the analytical algorithms by ensuring that only relevant data fields are accessed, maximizing the benefits of the parallel processing capabilities of the FPGA and the high-throughput communication channels. The specification states that the disclosed system and method are implemented to increase the performance of analytic algorithms and optimize the rate at which data is presented to them.
• Addressing Bottlenecks: Employing multiple communication channels is a direct solution to overcome data transfer bottlenecks between the processing unit and memory, which is a common concern in high-performance data processing. The patent explicitly states that the architecture minimizes or eliminates typical processor/network wait states and optimizes instruction fetch memory cycles.

Therefore, the combination of a distributed compute node with a programmable logic component, DMA, data reformatting into a columnar structure, and multi-channel data transfer would have been obvious to a POSA seeking to improve data processing and analytics performance.

Claim 11

Claim 11 describes a data processing system comprising:

1. A router module with a host interface and a node interface, communicatively coupled to a host compute system via the host interface.
2. A compute node comprising:
   a. A communications link to the node interface of the router module.
   b. A data store with records for a data processing operation.
   c. A programmable logic component to execute the data processing operation in cooperation with the data store.
   d. A node memory with data and instructions for the programmable logic component and for facilitating data communications.
   e. A data mover component to facilitate data communications between the programmable logic component and the node memory.
   f. A storage interface component to facilitate data communications between the programmable logic component and the data store.
3. The programmable logic component executes instructions to reformat a block of data (original records with multiple field types) into new records (each with a single field type).
4. The storage interface component uses a plurality of communications channels to transfer data between the programmable logic component and the data store.

Combination of Prior Art:

Many of the individual components of Claim 11 are well-known:

• Router Module and Compute Node Architecture: The overall system architecture of a host communicating with a router module, which in turn connects to compute nodes, is common in distributed systems and network-attached storage (NAS) or storage area networks (SAN). CPC class G06F3/067 (Distributed or networked storage systems, e.g., storage area networks [SAN], network attached storage [NAS]) directly covers this infrastructure. The patent's FIG. 1 illustrates this system.
• Data Store and Programmable Logic Component: The integration of a data store (e.g., Flash memory) with a programmable logic component (e.g., FPGA) on a compute node is known for accelerating data access and processing. The patent describes data store 143 as a mass data storage component and compute array 142 as potentially being an FPGA.
• Node Memory and Data Mover Component: The inclusion of local node memory and DMA components within a compute node for efficient data handling between the programmable logic component and node memory is standard practice in embedded and high-performance computing designs.
• Storage Interface Component with Multiple Channels: Storage interface components that manage access to data stores, often utilizing multiple communication channels for improved throughput, are also conventional. The patent describes data store interface 145n as managing access to data store 143 and potentially employing an ONFI protocol. The use of multiple channels is mentioned in connection with Flash memory access.
• Data Reformatting: As discussed for Claim 1, reformatting data into a columnar format to optimize analytical operations is a known technique.

Motivation for Combination:

A POSA would be motivated to combine these elements to create a high-performance data processing system capable of handling large datasets efficiently.

• Integrated High-Performance Storage and Compute: The integration of a data store directly with a programmable logic component on a compute node, managed by a dedicated storage interface component, reduces data movement overhead and latency often encountered in traditional architectures where storage is remote from the processing unit. The patent highlights the goal of minimizing or eliminating typical processor/network wait states.
• Leveraging Data Reformatting in Hardware: Implementing the data reformatting directly within the programmable logic component (e.g., FPGA) allows for "on-the-fly" optimization of data for analytical tasks, further boosting performance by presenting data to the processing unit in its most efficient form.
• Scalability and Throughput: The router module enables the system to scale by connecting multiple compute nodes. The use of multiple communication channels by the storage interface component directly addresses the need for high-throughput data transfer, a critical aspect for systems dealing with "massive amounts of data."

The combined features of a distributed system with dedicated compute nodes, local high-speed storage, reconfigurable logic for data reformatting, and multi-channel communication represent an obvious architectural approach for a POSA aiming to build a high-performance data analytics platform.

Claim 20

Claim 20 describes a data processing system comprising:

1. A management node with a host interface and a node interface, communicatively coupled to a host compute system.
2. A memory-supported compute node communicatively coupled to the management node, comprising:
   a. A data store.
   b. A programmable logic component to execute data processing operations.
   c. A node memory with data and instructions.
3. A pipeline of one or more additional compute nodes, each serially connected to the memory-supported compute node (or an upstream node) via a communications link, and each comprising a respective communications link and processing resources to execute a respective additional operation.
4. The system initiates an execution pipeline by loading a bit stream with an instruction set into the programmable logic space of each compute node.
5. A first operation is executed at the initiating node using the bit stream and data from its memory store, with results passed to the next node.
6. Each subsequent node executes a respective additional operation using the bit stream and results from the preceding operation.

Combination of Prior Art:

• Management Nodes and Distributed Compute Nodes: The concept of a management node overseeing and orchestrating tasks across multiple compute nodes is a standard pattern in distributed computing and cluster architectures.
• Pipelined Processing: Pipelining, where a series of processing stages are arranged such that the output of one stage becomes the input of the next, is a well-known technique for improving throughput in various processing contexts, including data processing and algorithm execution. CPC class G06F9/3867 (Concurrent instruction execution, e.g., pipeline or look ahead using instruction pipelines) is relevant here. The patent itself states that "one or multiple compute nodes operating in parallel (and in series, in some cases, as described below), each of which may be configured as a pipeline of computational elements".
• Programmable Logic Components and Bit Streams: Using programmable logic components (like FPGAs) and loading them with "bit streams" that contain instruction sets for specific algorithms is inherent to the operation of such devices. The patent explicitly describes loading bit streams into the FPGA fabric of compute array 142.
• Serial Connection of Compute Nodes: Connecting compute nodes serially, forming a "stack" or "tier" where data flows from one to the next, is a recognized way to implement a processing pipeline. FIG. 1 and FIG. 4 of the patent illustrate this serial coupling via communications links 149.
• Passing Intermediate Results: The passing of intermediate results from one stage of a pipeline to the next is a fundamental aspect of pipelined processing.

Motivation for Combination:

A POSA would be motivated to combine these elements to execute complex algorithms on large datasets with high throughput and efficiency.

• Accelerating Multi-Stage Algorithms: For algorithms that involve multiple sequential steps or transformations, a pipelined architecture allows each step to be performed concurrently on different parts of the data, significantly increasing the overall processing speed. The patent emphasizes the creation of "a fully parallelized dataflow environment which exhibits extremely high performance for analyzing massive amounts of data".
• Specialization of Compute Nodes: Each compute node in the pipeline can be specifically configured (via its bit stream) to perform a particular stage of the algorithm, leading to optimized resource utilization and potentially higher performance for each individual step. The architectural framework "generally contemplates one or multiple compute nodes operating in parallel (and in series, in some cases, as described below), each of which may be configured as a pipeline of computational elements that can be configured and operative to implement a variety of algorithms or other data processing operations."
• Scalability for Complex Tasks: The modular nature of compute nodes in a pipeline allows for scaling the processing capacity by adding more nodes, making the system adaptable to increasingly complex or data-intensive algorithms.

The integration of a management node, memory-supported compute nodes, and a pipeline of serially connected additional compute nodes, where a bit stream defines the pipelined algorithm execution and results are passed sequentially, represents an obvious approach for a POSA to achieve high-performance, scalable execution of multi-stage algorithms in a distributed environment.