Obviousness

The current date is May 21, 2026.

Obviousness Analysis of US Patent 11740801 under 35 U.S.C. § 103

This analysis identifies combinations of prior art that would render the claims of US patent 11740801 obvious to a person having ordinary skill in the art (POSITA). The patent focuses on cooperative flash management, where a host and a memory controller share responsibility for managing non-volatile (NV) memory, particularly by leveraging metadata about wear and data persistence, and by enabling the host to directly address physical subdivisions of memory.

The prior art cited in US11740801B1 includes several patents:

• US9652376B2
• US9229854B1
• US10642505B1

These prior art documents are generally related to memory management, data placement, and wear leveling in storage systems, especially those utilizing non-volatile memory like flash. The core inventive concept of US11740801B1 revolves around the cooperative aspect of management, specifically the memory controller providing detailed metadata to the host, and the host using that metadata to issue direct physical address commands, thereby reducing or eliminating the need for a Flash Translation Layer (FTL) at the controller.

Motivation to Combine Prior Art References

A POSITA in the field of memory systems, driven by known challenges in flash memory management (such as wear leveling, write amplification, and FTL overhead), would be motivated to combine existing techniques to improve performance, endurance, and efficiency. The primary motivations would include:

1. Reducing FTL Overhead and Latency: FTLs in flash controllers introduce complexity, overhead, and latency due to logical-to-physical address translation and background garbage collection/wear leveling operations. A POSITA would seek ways to offload or simplify these functions to improve overall system performance.
2. Improving Wear Leveling and Endurance: Flash memory has limited program/erase (P/E) cycles. More granular and intelligent wear leveling, especially with host-level awareness of data "hotness" and device wear, would extend the lifespan of flash devices.
3. Enhancing Data Placement Decisions: Optimizing where data is written (e.g., "hot" data to less-worn blocks, "cold" data to more-worn blocks) directly impacts endurance and read/write performance.
4. Increasing Host Control and Flexibility: Giving the host more direct control over physical memory management could allow for system-level optimizations that a black-box flash controller cannot achieve.

Obviousness Combinations for Independent Claims

Independent Claim 1 (Method Claim):
This claim focuses on a method where a memory controller maintains metadata (wear and persistence information) for physical subdivisions, sends it to a host, and the host uses this metadata to issue direct physical address commands for memory operations, bypassing L2P translation at the controller.

• Combination: US9652376B2 in view of US9229854B1 and US10642505B1 (and general knowledge of flash management)

  • US9652376B2 ("Flash memory controller with host-managed block erasure and wear leveling") explicitly teaches a flash memory controller that manages wear leveling and exposes certain management functions to a host. It discusses a "cooperative flash memory controller" that provides status information to the host and can receive commands from the host for memory operations, including wear leveling. It also refers to tracking per-data metrics (like hot/cold status) and wear metrics (like erase counts) for memory locations. The patent describes the host receiving information from the controller and using it to influence data placement and migration, including identifying data to move based on hot/cold status and selecting destination locations based on wear. The concept of the host being involved in flash management to some degree, including wear leveling, is central to US9652376B2.

  • US9229854B1 ("System and method for managing data in a memory system") further elaborates on managing data placement based on per-data metrics (e.g., age, hot/cold status) and wear metrics of memory locations. It describes a host and/or memory controller tracking hot/cold information and wear data to match data to storage locations, including moving "hot" data to less worn memory or "cold" data to more worn memory. This reference strengthens the motivation for the host to be aware of and utilize both data persistence and wear information.

  • US10642505B1 ("Cooperative flash memory management in a multi-controller, multi-tier memory system") describes a cooperative memory controller that makes metadata available to a host to assist with memory management. It also discusses the host taking or scheduling action based on this data, including commanding migration operations. The patent explicitly states that this infrastructure can "substantially eliminate the need for a flash memory controller to implement a flash translation layer (FTL)" by enabling the host to issue write commands "targeted to specific physical locations in flash memory". This directly addresses the "without requiring the memory controller to translate a logical address to a physical address" element of Claim 1.

  • Motivation for Combination: A POSITA, seeking to optimize flash memory usage and overcome FTL limitations, would be motivated to combine the host-involved wear leveling and data placement strategies of US9652376B2 and US9229854B1 with the explicit FTL-bypassing, direct physical addressing, and metadata sharing capabilities described in US10642505B1. The existing prior art already describes the problem (FTL overhead, wear leveling challenges) and offers pieces of the solution (host involvement, tracking metadata). US10642505B1 specifically details the mechanism of providing metadata to the host and allowing direct physical addressing to "substantially eliminate" the FTL, which directly anticipates or renders obvious the claimed method.

Independent Claim 16 (Memory Controller Claim):
This claim describes a memory controller with storage for metadata (wear and persistence) for physical subdivisions, an interface to send this metadata to a host upon command, and logic to receive host commands for memory operations on specific physical subdivisions without L2P translation.

• Combination: US9652376B2 in view of US10642505B1 (and general knowledge of flash controller design)

  • US9652376B2 describes a flash memory controller that stores metadata (including wear and per-data metrics) and interacts with a host for management tasks. The controller is capable of providing status information and receiving commands for memory operations.

  • US10642505B1 explicitly details a cooperative memory controller architecture where the controller "stores information specific to each of plural subdivisions of memory, and makes data based on that stored information accessible to the host to assist with host management of memory". It further states that the memory controller has "interface logic that permits a host to request any of these pieces of information by issuing respective commands". Crucially, it describes the host issuing "new write commands that are targeted to specific physical locations in flash memory, thus substantially avoiding the need for translation at a memory controller". This directly covers the storage of metadata, the interface to send it, and the ability to receive and execute direct physical address commands.

  • Motivation for Combination: A POSITA designing a flash memory controller, aware of the advantages of host-driven management from US9652376B2, would readily integrate the specific architectural features of US10642505B1. The goal would be to build a controller that enables the cooperative management described in the method claims, particularly the direct physical addressing by the host. The combination of a controller capable of tracking and reporting relevant metadata (wear, persistence) with an interface designed to facilitate host queries and direct physical commands (as explicitly laid out in US10642505B1) would be an obvious step for a POSITA to achieve the desired system-level efficiencies.

Independent Claim 22 (Memory System Claim):
This claim describes a memory system comprising a host and a memory controller, where the controller manages NV memory, stores metadata (wear and persistence), and has an interface to communicate this metadata to the host. The host has logic to receive this metadata and issue direct physical address commands, which the controller executes without L2P translation.

• Combination: US9652376B2 in view of US9229854B1 and US10642505B1 (and general system design principles)

  • This claim is a system-level embodiment of the method and controller claims. The individual components (host, memory controller, NV memory) and their cooperative interactions are all taught or made obvious by the combination of the prior art references discussed above.

  • US9652376B2 establishes the concept of a cooperative system where a host and flash controller work together for memory management.

  • US9229854B1 reinforces the use of both per-data and wear metrics in this cooperative management context.

  • US10642505B1 brings together the host's role in receiving metadata and issuing direct physical commands, and the controller's role in providing this metadata and executing those commands without internal L2P translation, explicitly forming a "memory system" with these characteristics. The patent states: "The host uses this information to issue new write commands that are targeted to specific physical locations in flash memory, thus substantially avoiding the need for translation at a memory controller, and reducing the likelihood of uneven wear." This describes the host logic to receive metadata and issue direct commands, and the controller's configuration to execute them without L2P translation.

  • Motivation for Combination: A POSITA designing a comprehensive memory system would integrate the cooperative management principles from US9652376B2 and US9229854B1 with the specific host-controller interface and FTL-bypassing architecture of US10642505B1. The motivation is to create a more efficient, durable, and performant flash-based storage system by distributing management intelligence and enabling direct control where beneficial. The combination would naturally lead to a system where the host is equipped to leverage the detailed information provided by the controller to make optimal physical placement decisions, thereby realizing the benefits of reduced FTL overhead and enhanced wear leveling.

In summary, the key elements of US11740801B1—cooperative flash management, memory controller providing metadata (wear and persistence), host using this metadata, and host issuing direct physical address commands that bypass L2P translation at the controller—are individually taught and, more importantly, explicitly combined in their functionality and intent within the collective teachings of US9652376B2, US9229854B1, and particularly US10642505B1. A POSITA would have a clear motivation to combine these references to achieve improved flash memory management.