Obviousness

Obviousness Analysis under 35 U.S.C. § 103 for US Patent 11709772

This analysis identifies combinations of prior art references that would render the independent claims of US Patent 11709772 obvious to a person having ordinary skill in the art (POSITA) as of the priority date of January 28, 2013. The invention's core contributions lie in the host's awareness of multi-plane memory geometry, host-directed physical address assignment for optimized multi-plane access, streamlined host-issued commands, and cooperative flash management.

A POSITA in the field of non-volatile memory systems around 2013 would have understood the architecture of NAND flash memory, including the concepts of planes, erase blocks (EUs), and pages. They would also be familiar with the challenges of NAND flash, such as P/E asymmetry, wear-out, and the performance overhead associated with Flash Translation Layers (FTLs) typically residing within the memory controller. The general goal of optimizing performance, reducing latency, and extending endurance in SSDs was well-known.

Combinations of Prior Art References

While specific prior art documents are not explicitly provided within the "Prior Art" section beyond general keywords and an earliest priority date, the patent itself discusses the state of the art. Based on this, a hypothetical combination of general knowledge in the field (acknowledged by the patent itself) and publicly available information prior to the priority date would likely lead to the claimed invention.

The patent US11709772 acknowledges several aspects as existing prior art or common problems:

• NAND flash memory devices with programming and erasing latencies and P/E asymmetry.
• Bus management techniques like interleaving requests to multiple devices to hide latency.
• Multi-plane designs permitting parallel access, but with "addressing and/or timing restrictions," typically limiting overlapping multi-plane access to situations where a common or base address is used for all planes. This often meant benefits were restricted to multi-plane writes by a memory controller for bandwidth management, with inefficient read access.
• Logical-to-physical (L2P) translation layers at the memory controller creating additional latency.

Therefore, for an obviousness argument, one would look for prior art that addresses these acknowledged limitations.

Proposed Combination 1: Existing Multi-plane Architectures + Host-Side FTL/Address Management + Cooperative Flash Management

References:

1. Conventional NAND flash memory devices with multi-plane capabilities: As acknowledged by US11709772 (e.g., "multi-plane designs have emerged which permit accesses to data stored in parallel planes or arrays"). This art would teach a multi-plane memory device managed by a memory controller.
2. Prior art disclosing host-side or cooperative Flash Translation Layers (FTLs) or host-managed physical addressing schemes for non-volatile memory: Prior to 2013, the concept of offloading FTL functionality, or at least portions of it, to the host for performance benefits and application-specific optimization was an active area of research and development in solid-state storage. Such references would teach a host interacting with a memory controller and seeking to optimize memory access.
3. Prior art disclosing cooperative memory management tasks (e.g., garbage collection, wear leveling, defect management) between a host and a memory controller: The idea of sharing responsibilities between a host and a memory controller to reduce overhead on the controller and improve overall system performance was a known technique in storage systems.

Reasoning for Obviousness:

A POSITA, motivated by the recognized limitations of conventional multi-plane NAND flash (inefficient reads, latency from controller-side FTLs, and the desire to improve performance and endurance), would have found it obvious to combine these elements.

• Motivation to expose memory geometry to the host: Knowing that multi-plane operations in conventional systems were restricted by "addressing and/or timing restrictions" and often limited to common base addresses, a POSITA would be motivated to expose the "memory geometry, including dies present and/or whether memory supports multi-plane access" to the host. This exposure would enable more intelligent data placement. The patent itself states, "a memory controller exports memory array/die/device geometry, and therefore has an option to educate one or more hosts on multi-array, multi-die or multi-plane capabilities of each managed memory array". This implies that the capability to expose this information already existed or was a straightforward extension for a memory controller.
• Motivation for host-directed physical address assignment: With the multi-plane geometry information, a POSITA would logically empower the host to "control physical address assignment to organize memory layout". This is a direct response to the problem of inefficient multi-plane read access and the overhead of controller-side FTLs, as the host could "direct new writes of data based on application or system level needs" and place "certain data types (e.g., consecutive media data)" consistently with multi-plane addressing restrictions. This allows the host to "plan for pipelined use of a memory bus in a manner that optimizes the retrieval of related data".
• Motivation for host-issued, streamlined multi-plane commands: To effectively utilize host-directed physical address assignments, a POSITA would devise "a single command or fused series of commands" from the host to the memory controller to manage multi-die/multi-plane access. This directly addresses the latency issue caused by complex address translation at the memory controller, leading to "streamlined interleaving across dies or devices" by bypassing "binary search trees and other complex translation functions". The patent suggests this could be supported by "extensions to a conventional command structure (e.g., NVMe for NAND flash memory)", implying that such extensions would be within the skill of a person in the art.
• Motivation for cooperative flash management: Recognizing that flash management tasks (GC, WL, DM) consume memory controller bandwidth and interfere with host requests, a POSITA would be motivated to introduce "cooperative functions that help reduce the need for complex L2P translation processes" and permit the "host to directly assume scheduling of many flash management functions that might interfere with (i.e., compete with) host-directed writes". The memory controller could provide necessary "metadata" (e.g., page utilization, wear data, cold data status) to the host in response to queries or asynchronously, allowing the host to schedule operations like "delegated copy operations" without requiring data movement to/from the host. This reduces "IO bandwidth and other system resources" consumption.

Therefore, combining the known multi-plane capabilities of NAND flash with existing knowledge about host-side FTL principles and cooperative management schemes, a POSITA would have been motivated to design a system where the memory controller exposes multi-plane geometry to the host, enabling the host to perform intelligent physical data placement for optimized multi-plane access (especially reads) and to issue streamlined multi-plane commands, while also engaging in cooperative flash management to improve overall system efficiency and reduce latency. The benefits of such a combination (improved throughput, reduced latency, better bus utilization) would have been readily apparent and desirable.

The patent itself outlines the problem and solution in a way that suggests a logical progression for a skilled artisan: "Applied to multi-plane memory a need exists for techniques that permit effective use of multi-plane capabilities notwithstanding device IO and addressing restrictions. The present invention satisfies these needs and provides further, related advantages." This statement, coupled with the detailed description of "conventional" issues, reinforces the idea that a POSITA would recognize these problems and be motivated to find solutions through known approaches of distributed intelligence and explicit resource management.