Prior art

To identify the most relevant prior art for US patent 11681614, I will review the citations listed in the patent document itself. The USPTO provides tools for searching patents and their citations.

Based on the provided patent text, US11681614B1 claims priority from two earlier US patent applications:

1. US13/767,723

   • Full Citation: US9652376B2
   • Publication/Filing Date: Priority claimed from 2013-02-14. US9652376B2 was granted on May 16, 2017.
   • Brief Description: US9652376B2 is titled "Storage device with subdivisions, subdivision query, and write operations," same as US11681614B1. This suggests it covers very similar subject matter. The patent discusses a memory controller that maintains usage information for physical subdivisions of memory and responds to host queries, with the host then issuing write commands specifying physical addresses.
   • Potential Anticipation (35 U.S.C. § 102): Given the identical title and priority claim, US9652376B2 likely anticipates many, if not all, of the claims in US11681614B1, especially if the claims in 11681614B1 do not introduce novel features beyond what was disclosed in 9652376B2. It would serve as direct prior art for all claims that do not present a patentable distinction.

2. US14/047,193

   • Full Citation: US9229854B1
   • Publication/Filing Date: Priority claimed from 2013-10-07. US9229854B1 was granted on January 5, 2016.
   • Brief Description: US9229854B1 is titled "Managing flash memory with host-provided physical address targets and memory controller data access functions." This patent also focuses on memory management where a host provides physical addresses for write operations. It discusses a memory controller that performs low-level data access functions and assists the host with memory management tasks by providing information about the physical memory.
   • Potential Anticipation (35 U.S.C. § 102): US9229854B1, with its focus on host-provided physical addresses and cooperative memory controller functions, appears to directly anticipate the core inventive concepts of US11681614B1, particularly Independent Claims 1, 7, 14, and 20, which revolve around the host specifying physical addresses for write operations after querying the memory controller for subdivision-specific usage information.

It is important to note that since US11681614B1 claims priority from these two earlier patents, the examination process for US11681614B1 would have considered these as its own lineage, meaning the claims of 11681614B1 should ideally be distinct enough to overcome these earlier disclosures. However, for a 35 U.S.C. § 102 analysis, these patents represent highly relevant prior art that would likely anticipate claims in 11681614B1 if those claims are not sufficiently novel over what was previously patented by the same assignee and inventors.