Obviousness

Obviousness Analysis of US Patent 11550512 under 35 U.S.C. § 103

This analysis evaluates the obviousness of US patent 11550512, titled "Analytics, algorithm architecture, and data processing system and method," by considering combinations of prior art concepts and known engineering principles that a person having ordinary skill in the art (POSA) would have been motivated to combine prior to the patent's earliest priority date of February 6, 2019. The "Prior art keywords" provided for this patent are "data, node, compute, memory, algorithm," indicating the general technological landscape. The patent itself describes limitations of conventional systems, which implicitly define the scope of the prior art.

1. General Scope and Content of the Prior Art

Based on the patent's own problem statements and the provided prior art keywords, the relevant prior art encompasses:

• Distributed Computing Architectures: Systems comprising multiple processing units (nodes) collaborating with a host computer for data processing, aiming to offload computational tasks.
• Programmable Logic Components: The use of Field-Programmable Gate Arrays (FPGAs) or similar reconfigurable hardware for accelerating specific computational tasks. The patent mentions FPGAs as components in host systems (Host compute system 199) and compute arrays (compute array 142).
• High-Performance Data Storage: The increasing use of solid-state devices (SSDs) such as Flash memory due to their decreased latency compared to traditional spinning media, especially in "cycle-intensive applications".
• Efficient Data Movement: Techniques like Direct Memory Access (DMA) for facilitating high-speed data transfers between processing units and memory components, thereby reducing CPU overhead.
• Data Structures and Reformatting: Conventional row-oriented data record structures (illustrated as FIG. 10 in the patent) were known, as were concepts of reformatting or organizing data (e.g., columnar storage in databases) to optimize performance for analytical queries.
• Algorithm Execution and Pipelining: Methods for loading and executing algorithms on processing units, and the concept of pipelined processing where complex tasks are broken down into sequential stages for increased throughput.
• Multi-channel Memory Access: Utilizing multiple communication channels to enhance bandwidth and reduce latency when accessing memory components, particularly Flash memory with its multiple Logical Units (LUNs) or planes.

2. Motivation to Combine Prior Art Elements

The overarching motivation for a POSA in the field of high-performance data processing and analytics would be to improve performance, increase throughput, reduce latency, and enhance scalability of data processing operations, especially for "Big Data" and other resource-intensive applications. The patent explicitly identifies issues such as "typical processor/network wait states," the need to "optimize instruction fetch memory cycles," and the goal to "analyze data that are streamed from an attached or associated data store at the maximum rate at which the data can be accessed or streamed by the storage subsystem". These identified problems directly motivate the combination of known technologies to achieve improved solutions.

3. Obviousness Analysis of Independent Claims

We will analyze the independent claims, identifying how known prior art elements would be combined by a POSA motivated by the aforementioned goals.

Claim 1: A method of executing data processing operations...

This claim describes a method involving a compute node with a programmable logic component (e.g., FPGA), a data mover component (e.g., DMA), and data reformatting for single field types, utilizing multiple communication channels.

• Combination: A POSA, motivated to accelerate data analytics and overcome I/O bottlenecks prevalent in "Big Data" processing, would find it obvious to combine:

  1. Distributed compute nodes with host independence: It was known to offload processing from a host to specialized compute nodes to distribute workload and improve scalability.
  2. Programmable logic components (FPGAs): FPGAs were well-established for accelerating specific, repetitive data processing tasks where general-purpose CPUs were inefficient.
  3. Data mover components (DMAs): DMAs were a standard technique for efficient, high-speed data transfer between memory and processing units (including FPGAs) without CPU intervention, crucial for reducing "processor/network wait states".
  4. Data reformatting for analytical efficiency: The concept of reformatting data from a row-oriented structure (like FIG. 10) to a columnar-like structure where "new records, each new record comprising a plurality of fields of a single field type" (similar to FIG. 11) was known in analytical databases and data warehousing to improve query performance for specific field types.
  5. Utilizing a plurality of communications channels: Employing multiple parallel data channels is a fundamental engineering approach to increase bandwidth and throughput for data transfer between high-speed components like FPGAs and memory/storage.

• Motivation: The motivation to combine these elements is clear: to leverage the specialized acceleration of FPGAs, the efficiency of DMAs, and the query performance benefits of columnar data storage, all interconnected with high-bandwidth multi-channel communication, to achieve "increased performance of analytic algorithms" and "optimize or maximize the rate at which data may be correctly presented to an analytic algorithm". Applying data reformatting (item 4) on a programmable logic component (item 2) using efficient data movement (item 3) and high-bandwidth channels (item 5) within a dedicated compute node (item 1) directly addresses the goal of accelerating analytical processing on large datasets.

Claim 10: A data processing system operative in cooperation with a host compute system...

This claim describes a system comprising a router module, a compute node with a communications link, data store, programmable logic component, node memory, data mover component, and storage interface component, where the storage interface uses multiple channels for data transfer.

• Combination: A POSA designing a high-performance system for data analytics, seeking to integrate fast storage with accelerated processing, would find it obvious to combine:

  1. A router module connecting a host to compute nodes: Standard practice in distributed systems to manage communication and resource allocation.
  2. Compute nodes as accelerator cards/modules: It was known to deploy specialized processing units (compute nodes) with local resources (memory, storage) as accelerator cards to offload computation from a host.
  3. Local data store (e.g., Flash memory): Tightly coupling high-speed Flash memory (data store 143) to the compute node was a known way to minimize I/O latency, as Flash memory was "gaining popularity in cycle-intensive applications".
  4. Programmable logic component (FPGA) on the compute node: Known for accelerating data processing tasks.
  5. Node memory and data mover component (DMA): Essential components for supporting the FPGA and enabling efficient data transfers between the FPGA and local memory/storage.
  6. Storage interface component: A controller (e.g., Flash controller, ONFI protocol) to manage access to the data store.
  7. Plurality of communications channels within the storage interface: Flash memory commonly offers multiple internal LUNs or planes that can be accessed in parallel. Utilizing multiple channels in the storage interface (data store interface 145 n) was a known technique to exploit this parallelism, enabling "interleaving... to have a positive effect on overall throughput" and "fully saturat[ing]... bandwidth for a given channel".

• Motivation: The motivation is to construct a scalable and high-throughput data processing system that fully exploits the speed of modern solid-state storage (Flash) by integrating it tightly with reconfigurable hardware acceleration (FPGA) within dedicated compute nodes. The use of multiple communication channels for the storage interface is directly motivated by the desire to "maximize[] data output" from Flash memory and "decrease or eliminate wait times typically caused by Flash... read delays or latency".

Claim 13: A data processing system operative in cooperation with a host compute system... (with a pipeline)

This claim describes a system with a management node, a memory-supported compute node, and a pipeline of one or more additional serially connected compute nodes, each with programmable logic and a data store.

• Combination: A POSA seeking to execute multi-stage algorithms or process streaming data efficiently would find it obvious to build upon the system of Claim 10 by:

  1. Management node and memory-supported compute node: As described in Claim 10, these are standard elements for a distributed accelerator system.
  2. Pipelined architecture with serially connected compute nodes: Pipelining is a fundamental computer architecture technique for enhancing throughput by allowing different stages of a process to operate concurrently on different data elements. Serially connecting dedicated processing nodes (each a "compute node" with programmable logic and data store) is the direct way to implement such a pipeline for distributed data processing. The patent states that the architectural framework contemplates "one or multiple compute nodes operating in parallel (and in series, in some cases, as described below), each of which may be configured as a pipeline of computational elements".

• Motivation: The motivation is to achieve higher overall throughput and lower effective latency for complex algorithms that can be broken into sequential steps. By dedicating separate compute nodes (each with its own FPGA for acceleration and local data store) to different stages of an algorithm and serially connecting them, a POSA would aim to overlap computation and data transfer, thereby maximizing the utilization of processing resources and significantly speeding up the execution of multi-stage data processing tasks.

Claim 17: A method of executing an algorithm in a distributed processing compute environment... (with a pipeline)

This claim describes a method for executing an algorithm using the pipelined compute node architecture of Claim 13, including loading bitstreams and passing results serially.

• Combination: A POSA tasked with optimizing the execution of multi-stage algorithms in a distributed environment would find it obvious to apply known pipelining principles to programmable logic systems by:

  1. Structuring the algorithm for pipelined execution: Breaking down an algorithm into discrete, sequential operations suitable for execution on separate stages.
  2. Mapping operations to serially coupled compute nodes: Assigning each sequential operation to a dedicated compute node in a serial pipeline, where each node has programmable logic (FPGA) and local memory/storage.
  3. Configuring programmable logic with bitstreams: Loading specific bitstreams into the FPGAs of each node to implement the assigned algorithmic stage, which is the standard method for configuring FPGAs.
  4. Sequential data processing and result passing: Performing the first operation at an initiating node and then passing intermediate results to the next node in the pipeline for subsequent operations, which is the defining characteristic of a pipeline.

• Motivation: The motivation is to efficiently execute complex algorithms on large datasets by leveraging the parallel and overlapping execution inherent in pipelined architectures. By configuring each stage of the pipeline on a dedicated compute node with accelerated programmable logic, a POSA would aim to achieve maximum throughput, especially for continuous data streams or iterative processes, thereby overcoming the "computational (and data record access) overhead" noted in prior methods.

In summary, the US11550512 patent discloses a system and method that combine individually known components and techniques (distributed computing, FPGAs, Flash memory, DMAs, multi-channel access, data reformatting, and pipelining) to address known performance limitations in data processing and analytics. A POSA, driven by the persistent and well-understood need to improve speed, efficiency, and scalability in this field, would have been motivated to combine these elements to achieve the claimed results.