Prior art

The USPTO website provides tools for searching patents, including Patent Public Search which allows searching by patent number.

The most relevant prior art for US Patent 11012252, "Active Ethernet Cable," as identified in its patent citations, is analyzed below. The analysis focuses on how these references potentially anticipate claims under 35 U.S.C. § 102, which generally relates to novelty and states that an invention cannot be patented if it was known or used by others before the applicant invented it, or if it was patented or described in a printed publication more than one year before the application date.

Here are the cited patents and their potential relevance:

1. US7049937B1

• Full Citation: US7049937B1, "Self-identifying cable for interconnecting electronic devices," granted May 23, 2006.
• Publication/Filing Date: June 11, 2002 (priority date).
• Brief Description: This patent describes a self-identifying cable that can communicate its characteristics (e.g., cable type, length) to connected devices. It focuses on the cable's ability to identify itself and potentially configure the devices for optimal performance.
• Potential Anticipation: This patent might anticipate aspects of US11012252B2 related to an "active" cable that provides information or performs functions beyond simple electrical conduction. Specifically, it could relate to the concept of a cable influencing or adapting communication based on its inherent properties, which in US11012252B2 involves equalization parameters. However, US7049937B1 doesn't explicitly mention transceivers performing clock and data recovery and re-modulation within the cable for signal regeneration, which is central to US11012252B2's independent claims.

2. US20070237464A1

• Full Citation: US20070237464A1, "Electrical-optical active optical cable," published October 11, 2007.
• Publication/Filing Date: April 10, 2006 (priority date).
• Brief Description: This publication describes an active optical cable that converts electrical signals to optical signals and vice-versa, allowing for longer transmission distances than passive electrical cables.
• Potential Anticipation: This reference introduces the concept of an "active" cable with integrated electronics to extend signal reach. While it focuses on optical conversion, the general idea of an active cable with integrated transceivers for signal regeneration could be seen as broadly anticipatory to the "active" nature of the Ethernet cable in US11012252B2. However, the specific electrical signal processing, clock and data recovery, and re-modulation of electrical signals for transit within an Ethernet cable, as described in US11012252B2's independent claims, are not directly addressed.

3. US7401985B2

• Full Citation: US7401985B2, "Electrical-optical active optical cable," granted July 22, 2008.
• Publication/Filing Date: April 10, 2006 (priority date).
• Brief Description: This patent is a granted version of US20070237464A1, describing an active optical cable for converting electrical signals to optical signals and back.
• Potential Anticipation: As a granted version of US20070237464A1, its potential anticipation is similar. It broadens the concept of an "active" cable but doesn't specifically detail the electrical domain signal conditioning (CDR and re-modulation with fixed equalization for host-facing links, and cable-dependent for internal links) that distinguishes US11012252B2.

4. US20130343400A1

• Full Citation: US20130343400A1, "Link training and training frame for 100gbps ethernet," published December 26, 2013.
• Publication/Filing Date: June 22, 2012 (priority date).
• Brief Description: This publication describes methods for link training and the use of training frames in high-speed Ethernet, particularly for 100 Gbps. Link training involves adapting equalization filters to combat channel non-idealities.
• Potential Anticipation: This reference is highly relevant as it describes link training and adaptive equalization within an Ethernet context. While US11012252B2 emphasizes fixed, cable-independent equalization for host interfaces and potentially cable-dependent or adaptive equalization for internal cable links (claims 2, 3, 12-14), US20130343400A1 focuses on adaptive equalization generally for high-speed Ethernet. The concept of training phases and equalization (as discussed in the detailed description of US11012252B2, referring to Figures 4 and 5) could be anticipated in a broader sense. However, the specific architecture of transceivers within the cable performing CDR and re-modulation on both inbound and transit data streams, and the distinct application of fixed vs. cable-dependent equalization parameters for different parts of the communication path as claimed in US11012252B2, may differentiate it.

5. US9230416B2

• Full Citation: US9230416B2, "Communication devices including a sensor configured to detect physical input," granted January 5, 2016.
• Publication/Filing Date: August 6, 2012 (priority date).
• Brief Description: This patent describes communication devices with sensors to detect physical input, such as cable insertion, and react accordingly. It broadly covers how devices interact with physical connections.
• Potential Anticipation: This patent might be relevant to the general interaction between a host device and a cable, particularly if the "active" nature of US11012252B2's cable involves detecting its presence or capabilities. However, it does not appear to directly anticipate the core claims of US11012252B2 regarding internal transceivers performing CDR and re-modulation for signal integrity within the cable.

6. US20140086264A1

• Full Citation: US20140086264A1, "Method for rapid pma alignment in 100gbase-kp4," published March 27, 2014.
• Publication/Filing Date: September 24, 2012 (priority date).
• Brief Description: This publication details methods for rapid Physical Media Attachment (PMA) alignment in high-speed Ethernet (100GBASE-KP4), which is part of the physical layer.
• Potential Anticipation: This reference relates to the physical layer operations of high-speed Ethernet, including PMA sublayer functions (which the transceivers in US11012252B2 may implement, as stated in its description). The techniques for rapid alignment could be relevant to the efficient operation of the transceivers. Similar to US20130343400A1, it provides context for high-speed Ethernet physical layer challenges and solutions but may not directly anticipate the specific active cable architecture with dual CDR/re-modulation stages and distinct equalization parameter strategies.

7. US20140146833A1

• Full Citation: US20140146833A1, "Pma-size training frame for 100gbase-kp4," published May 29, 2014.
• Publication/Filing Date: November 29, 2012 (priority date).
• Brief Description: This publication describes the use of PMA-sized training frames for 100GBASE-KP4 Ethernet to facilitate link training and equalization.
• Potential Anticipation: This builds on the concepts of link training and equalization for high-speed Ethernet (similar to US20130343400A1 and US20140086264A1) by specifying the use of particular training frames. The training phase, as mentioned in US11012252B2 (e.g., in relation to Figures 4 and 5, and controller 216), is a common aspect of high-speed serial communication. The specific content and application of these training frames within an active cable that performs CDR and re-modulation internally might differentiate US11012252B2.

8. US9322704B1

• Full Citation: US9322704B1, "Composite active optical cables," granted April 26, 2016.
• Publication/Filing Date: October 18, 2013 (priority date).
• Brief Description: This patent describes composite active optical cables, which integrate both optical and electrical components to manage power and signaling.
• Potential Anticipation: This further elaborates on "active" cables by combining optical and electrical aspects. While still focused on optical transmission, the idea of a composite active cable managing both signal and power might broadly relate to the active nature of the Ethernet cable in US11012252B2. However, the core claims of US11012252B2 are specific to electrical Ethernet cables and the detailed signal processing within them.

9. US9337993B1

• Full Citation: US9337993B1, "Timing recovery in a high speed link," granted May 10, 2016.
• Publication/Filing Date: December 27, 2013 (priority date).
• Brief Description: This patent describes methods and systems for timing recovery in high-speed communication links, which is crucial for accurate data reception.
• Potential Anticipation: This patent directly relates to "clock and data recovery" (CDR), a fundamental aspect of US11012252B2's independent claims. The techniques for timing recovery described could be seen as anticipating the CDR functions within the transceivers of the active Ethernet cable. However, US11012252B2's claims specify where and how CDR is applied (on both inbound and transit signals, with specific equalization strategies) within an active cable architecture, which might still represent a novel combination or application of known CDR techniques.

10. US20150334186A1

• Full Citation: US20150334186A1, "Coax Adaptor for Ethernet Physical Layer Transceiver," published November 19, 2015.
• Publication/Filing Date: May 15, 2014 (priority date).
• Brief Description: This publication describes an adapter that allows an Ethernet Physical Layer Transceiver (PHY) to operate over coaxial cable. It might involve signal conditioning for compatibility.
• Potential Anticipation: This reference pertains to adapting Ethernet signals to different physical media (coaxial cable), which inherently involves signal processing for compatibility. This could broadly relate to the idea of ensuring robust data transfer over a particular cable medium. However, US11012252B2 focuses on active processing within the Ethernet cable itself, with two stages of CDR and re-modulation, rather than an adapter for a different medium.

11. US20160197434A1

• Full Citation: US20160197434A1, "Flat ethernet cables and associated systems, devices, and methods," published July 7, 2016.
• Publication/Filing Date: January 5, 2015 (priority date).
• Brief Description: This publication describes the physical construction of flat Ethernet cables and systems associated with them.
• Potential Anticipation: This reference is primarily focused on the physical form factor of Ethernet cables. It does not appear to directly anticipate the active electronic components (transceivers performing CDR and re-modulation) or the specific equalization strategies central to US11012252B2's independent claims.

12. US20180241579A1

• Full Citation: US20180241579A1, "Power supply system, power sourcing equipment, and ethernet y cable," published August 23, 2018.
• Publication/Filing Date: April 9, 2015 (priority date).
• Brief Description: This publication describes power supply systems for Ethernet, including Y-cables that might provide power to devices or active components.
• Potential Anticipation: This reference addresses power delivery in Ethernet cables, which is a necessary aspect for "active" cables like the one in US11012252B2 (since its transceivers are "powered"). However, it does not describe the signal processing aspects (CDR, re-modulation, equalization) that form the core of US11012252B2's claims.

13. US20200280458A1

• Full Citation: US20200280458A1, "Active ethernet cable," published September 3, 2020.
• Publication/Filing Date: March 1, 2019 (priority date).
• Brief Description: This is a prior publication of US11012252B2, listing the same title, inventors, and assignee.
• Potential Anticipation: As a prior publication of the same patent, it is not considered prior art under 35 U.S.C. § 102 against its own granted claims, but rather part of the same patent family.

14. US20200280329A1

• Full Citation: US20200280329A1, "Active 1:n breakout cable," published September 3, 2020.
• Publication/Filing Date: March 1, 2019 (priority date).
• Brief Description: This publication describes an active breakout cable, such as a 1:4 breakout cable for Ethernet, which can adapt to different generations of Ethernet standards or split high-speed signals into multiple lower-speed lanes.
• Potential Anticipation: This is closely related to US11012252B2, as US11012252B2 itself discusses breakout cables in its detailed description (Figures 7 and 8). This reference focuses on the "breakout" aspect, but the underlying active cable technology with transceivers, CDR, and re-modulation is highly similar. Since it shares the same priority date and assignee, it is likely part of the same intellectual property portfolio rather than anticipating US11012252B2 under 35 U.S.C. § 102.

15. CN111641090A

• Full Citation: CN111641090A, "An active 1: n branch cable," published September 8, 2020.
• Publication/Filing Date: March 1, 2019 (priority date).
• Brief Description: This Chinese patent application describes an active 1:n branch (breakout) cable.
• Potential Anticipation: Similar to US20200280329A1, this is a related application from the same priority date and assignee, focusing on breakout cables. Its relationship to US11012252B2 is as a family member rather than prior art for novelty purposes.

In summary, many of the cited patents broadly deal with "active" cables, high-speed Ethernet, link training, and signal integrity. US20130343400A1, US20140086264A1, US20140146833A1, and US9337993B1 are particularly relevant as they address aspects of link training, equalization, and timing recovery in high-speed communication. However, the specific inventive contribution of US11012252B2 lies in the dual-stage CDR and re-modulation within the cable's connectors, coupled with the distinct application of fixed, cable-independent equalization for host interfaces and potentially cable-dependent equalization for the internal cable links. This specific architectural and parameter management approach within an active Ethernet cable is what differentiates US11012252B2 from the broader prior art.