Obviousness

US patent 10877233 claims a cable, a manufacturing method, and a communications method featuring active Ethernet cables with Data Recovery and Re-modulation (DRR) devices at each end. A core inventive feature lies in these DRR devices providing preset pre-equalization of electrical transit signals using transmit filter coefficient values stored in nonvolatile memories. This aims to enhance performance and reduce receiver-side equalization requirements, especially in high-speed, extended-length cables.

An analysis of prior art reveals combinations that would render the claims of US10877233 obvious to a person having ordinary skill in the art (PHOSITA) under 35 U.S.C. § 103.

Obviousness Combination: WO2018161273A1 (Credo Technology Group Ltd.) in view of US9385897B2 (Avago Technologies)

References:

1. WO2018161273A1: "Ethernet link extension method and device" (Priority Date: March 8, 2017). This PCT application, by the same assignee as US10877233, describes "Ethernet link extension" and "active Ethernet cables" which typically incorporate DRR-like functionality for signal re-timing and re-driving over extended distances. The background of US10877233 itself acknowledges that "Active ethernet cable (AEC) is a newly-designed cable that offers affordable high-bandwidth data transport over distance spans up to at least seven meters using hard-wired data recovery and remodulation (DRR) chips in the cable connectors". The patent further explicitly states that auto-negotiation in its contemplated embodiments "may be implemented as described in PCT/CN2017/075961" (WO2018161273A1). This establishes that active Ethernet cables with DRR devices, converting between host data streams and electrical transit signals, were known in the art, especially to the applicant.
2. US9385897B2: "Methods and apparatus for adapting transmitter equalization coefficients based on receiver gain adaptation" (Priority Date: July 18, 2012). This patent explicitly teaches adaptive transmitter equalization using transmitter equalization coefficients. It describes methods for "adapting transmitter equalization coefficients" and "storing transmitter equalization coefficients in a memory." The abstract of US9385897B2 further states that adaptively setting transmit equalization coefficients can "reduce power consumed by a receive equalizer."

Rationale for Obviousness:

Problem: The background of US10877233 highlights the increasing difficulty in assuring robust performance for per-lane bit rates beyond 50 Gbps over distances more than a couple of meters, noting that "increased channel attenuation and dispersion necessitates increasing levels of equalization, to the point that receiver power consumption and dissipation may reach prohibitive levels." The invention proposes "preset transmit-side equalization to provide enhanced performance and/or to reduce receive-side equalization requirements."

Motivation to Combine: A PHOSITA designing or improving active Ethernet cables (as generally taught by WO2018161273A1) to handle higher data rates and longer distances would be keenly aware of the power consumption challenges associated with extensive receiver-side equalization. US9385897B2 directly addresses this problem by teaching the use of transmit-side equalization with adaptable coefficients as a means to reduce receiver equalizer power consumption.

Therefore, a PHOSITA would have been motivated to combine the active Ethernet cable architecture and DRR functionality of WO2018161273A1 with the transmit-side equalization principles taught by US9385897B2. The goal would be to leverage the power-saving benefits of pre-equalization in the context of active Ethernet cables to overcome the stated power consumption limitations of receive-side equalization. Storing these empirically determined transmit filter coefficient values in nonvolatile memory (as explicitly taught by US9385897B2, "storing transmitter equalization coefficients in a memory") and then retrieving them at power-on (as described in US10877233B1, e.g., MCU loads parameters from Flash memory 207 into DRR's configuration registers 208 at power-on) would be an obvious design choice for a PHOSITA to ensure consistent and optimal cable performance without requiring a full re-training process every time the cable is powered up or re-connected. The process of "characterizing channel characteristics... to determine the transmit filter coefficient values; and storing the transmit filter coefficient values in the nonvolatile memories" after cable assembly (Claims 4, 11, 18 of US10877233) is a standard engineering practice for optimizing the performance of active cables and would be an obvious implementation detail when combining these references.

Specific Claim Elements:

• Claims 1, 8, 15 (DRR devices, electrical conductors, converting data streams): These elements are well-understood functions of active Ethernet cables designed for link extension and would be apparent from WO2018161273A1 and the general state of the art for active cables as acknowledged in US10877233 itself. The description of US10877233 defines DRR devices as performing "clock and data recovery (CDR) and re-modulation of data streams" and processing "data streams traveling in each direction", which is inherent to an "Ethernet link extension method and device".
• Claims 1, 8, 15 (Pre-equalization of electrical transit signals using transmit filter coefficient values): US9385897B2 explicitly teaches "adapting transmitter equalization coefficients" for "transmit equalization."
• Claims 1, 8, 15 (Stored in nonvolatile memories): US9385897B2 teaches "storing transmitter equalization coefficients in a memory." While not explicitly "nonvolatile," selecting nonvolatile memory for persistently storing optimized configuration settings in an active cable device (like a DRR device in WO2018161673A1) would be an obvious engineering choice to ensure that the pre-equalization settings are retained across power cycles and readily available upon boot-up.
• Claims 2, 9, 16 (Controller configures DRR device in response to power-on event, retrieving coefficients): This is an obvious implementation detail for utilizing stored parameters. US10877233 itself describes an MCU (206) that "loads equalization parameters from Flash memory 207 into the DRR device's configuration registers 208" at power-on. This mechanism for loading stored coefficients from memory at power-on to configure the equalization filters would be a routine design choice for a PHOSITA.
• Claims 3, 10, 17 (Programmed to use transmit coefficient values each time power is supplied): This directly flows from storing coefficients in nonvolatile memory and retrieving them at power-on, ensuring consistent performance.
• Claims 4, 11, 18 (Coefficients determined and stored after assembly, characterizing channel characteristics): US9385897B2 teaches "adaptively setting" and "adapting" coefficients, implying a determination process. The step of characterizing the specific cable after assembly to determine optimal equalization parameters and storing them for subsequent use is a logical and common practice in optimizing active cable performance.
• Claims 5, 12, 19 (Receiver-based equalization): US10877233 discusses receiver-based equalization (CTLE, FFE, DFE) in FIG. 4, which is a known technique. The patent states that pre-equalization "enables the use of far fewer taps in the receive filters, potentially enabling the FFE filter to be omitted entirely." Thus, combining transmit-side pre-equalization with (potentially simplified) receiver-based equalization would be an obvious design choice for a PHOSITA aiming for an optimal balance of performance and power efficiency.
• Claims 6, 13 (Twin-axial conductors): Twin-axial conductors are a known type of electrical conductor suitable for differential signals and reducing crosstalk, as described in US10877233, and thus represent an obvious material choice in the field.
• Claims 7, 14, 20 (DRR devices do not perform pre-equalization of host-facing data streams): This implies that pre-equalization is specifically for the internal cable channel, not the host interface, which is consistent with the problem of signal degradation within the cable over extended lengths, and a logical design decision to maintain compliance with host interface standards.

In summary, the combination of active Ethernet cable technology (WO2018161273A1) with known transmit equalization techniques that store coefficients in memory to reduce receiver power (US9385897B2), would lead a PHOSITA to the claimed invention with a reasonable expectation of success to achieve improved power efficiency and robust performance in high-speed, extended-length active Ethernet cables.

Additional Obviousness Consideration: US20200280458A1 (Credo Technology Group Limited)

While not strictly necessary given the strength of the WO2018161273A1 + US9385897B2 combination, US20200280458A1, "Active ethernet cable" (Priority Date: March 1, 2019), is also prior art to US10877233. This patent also from Credo Technology Group Limited, further reinforces the state of the art regarding active Ethernet cables and DRR devices for extending link distances. A PHOSITA would similarly be motivated to apply the transmit equalization teachings of US9385897B2 to the active Ethernet cables described in US20200280458A1 for the same reasons of power efficiency and performance enhancement.