Derivative works

Defensive Disclosure for US10771069

Publication Date: 2026-06-05

This Defensive Disclosure aims to broaden the public domain knowledge surrounding Field Programmable Gate Array (FPGA) systems with internal phase-locked loops, particularly concerning clock synchronization and phase matching. The objective is to proactively publish derivative variations of the technology described in US Patent 10771069, thereby establishing prior art that may render future incremental improvements by competitors obvious or non-novel under 35 U.S.C. § 102 and § 103. The focus is on extending the core concepts of phase-aligned data processing within FPGAs to various materials, operational extremes, application domains, emerging technologies, and failure modes.

Core Claim 1 Analysis and Derivatives

US Patent 10771069, Claim 1, generally describes an FPGA system featuring a deserializer, computational circuitry, a serializer, a phase detector, a phase controller, and an adjustable oscillator. The core inventive concept revolves around using a phase detector to measure the phase difference between a receiver-side clock and an interim transmitter-side clock, and then employing a phase controller and an adjustable oscillator to generate an adjusted wire rate clock signal for the serializer, thereby achieving phase matching of the transmitter-side clock. The following derivatives explore variations of this fundamental architecture.

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Derivative 1: Material & Component Substitution - Superconducting FPGA with Josephson Junction Oscillators

Enabling Description:
This derivative envisions the FPGA system of Claim 1 implemented using superconducting technology, specifically employing Niobium-based Josephson Junction (JJ) logic for the FPGA core, deserializer, serializer, computational circuitry, phase detector, and phase controller. The adjustable oscillator, typically a Voltage-Controlled Oscillator (VCO) in conventional silicon FPGAs, is substituted with a Josephson Junction Phase-Locked Loop (JJ-PLL) incorporating a Superconducting Quantum Interference Device (SQUID)-based or phase-slip oscillator.

The first and second reference clock pins would receive cryogenically stable reference clock signals. The deserializer converts the incoming serial data stream, now potentially operating at sub-terahertz frequencies due to the superconducting logic, into parallel data streams using rapid single flux quantum (RSFQ) gates. The computational circuitry, also based on RSFQ logic, performs operations at significantly higher clock rates (e.g., hundreds of GHz to THz) with drastically reduced power consumption and latency. The phase detector, implemented with JJ-based phase comparators, measures the phase difference between the receiver-side clock (derived from the deserializer's output) and the interim transmitter-side clock (generated by the JJ-PLL). The phase controller, an RSFQ finite state machine, processes this phase difference indicator signal and generates adjustment information as a digital flux quantum signal. This adjustment information is fed to the adjustable JJ-PLL, which then generates the wire rate clock signal for the serializer, precisely aligning the transmitter-side clock's phase in the superconducting domain. The entire system operates at cryogenic temperatures, typically 4 Kelvin or below, to maintain superconductivity.

graph TD
    Oscillator_Ref[Cryogenic Reference Oscillator] --> RefClkPin1[First Ref Clock Pin]
    Oscillator_Adj(Adjustable JJ-PLL) --> RefClkPin2[Second Ref Clock Pin]
    IO_Module_In[Cryogenic I/O Module (Serial In)] --> DataPin1[First Data Pins]
    DataPin1 --> Deserializer(JJ Deserializer)
    RefClkPin1 --> Deserializer
    Deserializer -- RXCLOCK (JJ Logic) --> PhaseDetector(JJ Phase Detector)
    Deserializer -- Parallel Data --> ComputationalLogic(JJ Computational Circuitry)
    ComputationalLogic -- Parallel Data --> Serializer(JJ Serializer)
    ComputationalLogic -- RXCLOCK (JJ Logic) --> Serializer
    Serializer -- TXCLOCK_Interim (JJ Logic) --> PhaseDetector
    PhaseDetector -- Phase Diff Signal (Flux Quanta) --> PhaseController(JJ Phase Controller)
    PhaseController -- Adjustment Info (Flux Quanta) --> Oscillator_Adj
    Oscillator_Adj -- Wire Rate Clock (JJ Logic) --> Serializer
    Serializer -- Serial Data --> DataPin2[Second Data Pins]
    DataPin2 --> IO_Module_Out[Cryogenic I/O Module (Serial Out)]

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Derivative 2: Operational Parameter Expansion - Ultra-High Frequency & Distributed Synchronization

Enabling Description:
This derivative describes the FPGA system of Claim 1 operating at extremely high frequencies (e.g., 200+ Gbps per serial lane, 10 GHz internal clock frequency) and extended to a distributed multi-FPGA architecture. Each FPGA node includes the core components: a deserializer, computational circuitry, serializer, phase detector, phase controller, and an adjustable oscillator. The deserializer and serializer transceivers are designed for 200 Gbps+ data rates, utilizing advanced SiGe or InP-based electro-optical components for conversion at the physical layer. The internal parallel data streams are extremely wide (e.g., 256 or 512 bits) operating at multi-GHz clock rates.

The novelty lies in the distributed phase synchronization. The phase controller on each FPGA node not only adjusts its local oscillator but also communicates its phase difference indicator signal and adjustment information to a central network timing controller and to adjacent FPGAs via a dedicated low-latency optical interconnect. This allows for a global phase alignment across multiple FPGAs, compensating for inter-FPGA link skews and environmental variations. The adjustable oscillator is a highly stable, digitally-controlled oscillator (DCO) with sub-picosecond phase resolution, capable of rapid frequency and phase adjustments. The phase detector samples at multi-GHz rates, providing granular phase difference measurements. The computational circuitry leverages highly pipelined architectures and custom hard IP blocks optimized for these extreme frequencies, avoiding any clock domain crossings by ensuring all local processing is phase-aligned.

graph TD
    SubGraph FPGA_A
        direction LR
        A_IO_IN[Serial Data In A] --> A_DES(Deserializer A)
        A_REF_CLK[Ref Clock A] --> A_DES
        A_DES -- RX_CLKA --> A_PD(Phase Detector A)
        A_DES -- Parallel Data A --> A_COMP(Computational Logic A)
        A_COMP -- Parallel Data A --> A_SER(Serializer A)
        A_COMP -- RX_CLKA --> A_SER
        A_SER -- TX_Interim A --> A_PD
        A_PD -- Phase Diff A --> A_PC(Phase Controller A)
        A_PC -- Adj Info A --> A_OSC(Adjustable OSC A)
        A_OSC -- WR_CLKA --> A_SER
        A_SER --> A_IO_OUT[Serial Data Out A]
    end
    SubGraph FPGA_B
        direction LR
        B_IO_IN[Serial Data In B] --> B_DES(Deserializer B)
        B_REF_CLK[Ref Clock B] --> B_DES
        B_DES -- RX_CLKB --> B_PD(Phase Detector B)
        B_DES -- Parallel Data B --> B_COMP(Computational Logic B)
        B_COMP -- Parallel Data B --> B_SER(Serializer B)
        B_COMP -- RX_CLKB --> B_SER
        B_SER -- TX_Interim B --> B_PD
        B_PD -- Phase Diff B --> B_PC(Phase Controller B)
        B_PC -- Adj Info B --> B_OSC(Adjustable OSC B)
        B_OSC -- WR_CLKB --> B_SER
        B_SER --> B_IO_OUT[Serial Data Out B]
    end
    A_PC -- Global Sync Req --> Central_NTC[Central Network Timing Controller]
    B_PC -- Global Sync Req --> Central_NTC
    Central_NTC -- Global Adj --> A_PC
    Central_NTC -- Global Adj --> B_PC
    A_OSC -- Cross-FPGA Link Sync --> B_OSC
    B_OSC -- Cross-FPGA Link Sync --> A_OSC

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Derivative 3: Cross-Domain Application - Precision Scientific Instrument Data Acquisition

Enabling Description:
This derivative applies the FPGA system of Claim 1 to high-precision scientific instrument data acquisition, specifically in contexts like particle accelerators or radio astronomy arrays where femtosecond-level synchronization across distributed sensors is critical.

The FPGA (e.g., a radiation-hardened variant) is deployed as a front-end data acquisition unit. The first serial data stream comprises raw sensor data (e.g., digitized RF signals from an antenna array or event data from particle detectors) transmitted over optical fiber links, requiring precise phase recovery. The first reference clock signal is a highly stable, externally disciplined clock (e.g., GPS-DO or atomic clock reference). The deserializer (implemented with hardened, low-noise components) recovers the high-speed data and a receiver-side clock. The computational circuitry performs initial filtering, timestamping, and preliminary event detection on the parallel data streams, synchronized to the receiver-side clock. The serializer transmits processed data and synchronized control signals (the second serial data stream) back to a central control unit.

The phase detector is an ultra-high-resolution time-to-digital converter (TDC) integrated into the FPGA fabric, capable of measuring phase differences with picosecond or even sub-picosecond precision. The phase controller (a custom, low-latency control loop in the FPGA logic) processes the TDC output to generate adjustment information. This information is fed to an on-chip adjustable, fractional-N PLL (the adjustable oscillator), which generates the wire rate clock signal for the serializer. The PLL is designed for exceptionally low jitter and phase noise, ensuring the transmitted data and synchronization signals maintain the required femtosecond-level phase coherence for distributed array processing or event correlation across the scientific instrument.

graph TD
    AtomicClock[Atomic Clock Reference] --> RefClkPin1[First Ref Clock Pin (FPGA)]
    SensorArray[Distributed Sensor Array] --> OpticalLinkIn[Optical Fiber Link]
    OpticalLinkIn --> DataPin1[First Data Pins (FPGA)]
    DataPin1 --> Deserializer(Hardened Deserializer)
    RefClkPin1 --> Deserializer
    Deserializer -- RX_CLOCK (Low Jitter) --> PhaseDetector(Integrated TDC Phase Detector)
    Deserializer -- Raw Parallel Data --> ComputationalLogic(FPGA Comp. Logic - Filtering/Timestamp)
    ComputationalLogic -- Processed Parallel Data --> Serializer(Hardened Serializer)
    ComputationalLogic -- RX_CLOCK --> Serializer
    Serializer -- TX_Interim (Low Jitter) --> PhaseDetector
    PhaseDetector -- Picosecond Phase Diff --> PhaseController(Custom Low-Latency Control Loop)
    PhaseController -- Digital Adjustment --> AdjustableOscillator(Fractional-N PLL)
    AdjustableOscillator -- Wire Rate Clock --> Serializer
    Serializer --> OpticalLinkOut[Optical Fiber Link]
    OpticalLinkOut --> CentralControl[Central Control Unit / Data Processor]

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Derivative 4: Integration with Emerging Tech - AI-Optimized Adaptive Phase Alignment

Enabling Description:
This derivative integrates the FPGA system of Claim 1 with an AI-driven optimization layer for adaptive phase alignment. The deserializer, computational circuitry, and serializer function as described.

The phase detector measures the raw phase difference. The phase controller, instead of a fixed-parameter control loop, incorporates a lightweight, embedded Machine Learning (ML) inference engine (e.g., a pre-trained neural network). This ML engine receives the phase difference indicator signal, along with additional telemetry data from the FPGA (e.g., internal temperature sensors, supply voltage monitors, data traffic load, age of components, external environmental sensors via IoT gateway) as inputs.

Based on these inputs, the ML engine dynamically predicts optimal adjustment information (e.g., precise bias voltage for a VCO, fine-grained divider ratios for a fractional-N PLL, or delay line tap settings). This adjustment information is then fed to the adjustable oscillator. Over time, the ML model can be periodically retrained (offline or with limited online learning) using historical performance data and observed phase drift patterns, allowing the system to proactively compensate for environmental variations, component aging, and workload-dependent jitter, achieving superior and more stable phase alignment than static control loops. This creates a self-optimizing phase alignment system. Furthermore, significant phase-alignment events, changes in configuration, and the ML model's confidence scores for adjustments are logged and immutably stored on a distributed ledger (blockchain) for auditability and certification in critical applications.

graph TD
    RefClkPin1[First Ref Clock Pin] --> Deserializer(Deserializer)
    DataPin1[First Data Pins] --> Deserializer
    Deserializer -- RX_CLOCK --> PhaseDetector(Phase Detector)
    Deserializer -- Parallel Data --> ComputationalLogic(Computational Circuitry)
    ComputationalLogic -- Parallel Data --> Serializer(Serializer)
    ComputationalLogic -- RX_CLOCK --> Serializer
    Serializer -- TX_Interim --> PhaseDetector
    PhaseDetector -- Phase Diff Signal --> ML_Controller(Embedded ML Inference Engine)
    ML_Controller -- Adjustment Info --> AdjustableOscillator(Adjustable Oscillator)
    AdjustableOscillator -- Wire Rate Clock --> Serializer
    FPGA_Telemetry[FPGA Telemetry (Temp, Voltage, Load)] --> ML_Controller
    IoT_Sensors[IoT Environmental Sensors] --> ML_Controller
    ML_Controller -- Logged Events/Adjustments --> Blockchain[Blockchain Ledger for Audit]
    ML_Controller -- Model Updates --> Cloud_ML_Platform(Cloud ML Platform for Retraining)

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Derivative 5: The "Inverse" or Failure Mode - Graceful Degradation to Frequency-Locked Low-Power Mode

Enabling Description:
This derivative describes an FPGA system according to Claim 1, but with an added "Failure Mode Manager" for graceful degradation and low-power operation. In normal operation, the system provides full phase alignment. However, if the phase detector continuously reports a phase difference exceeding a predefined high threshold for a sustained period (indicating loss of phase lock), or if a low-power mode is explicitly commanded, the Failure Mode Manager is activated.

Upon activation, the system transitions from phase-locked mode to a frequency-locked, low-power mode. In this mode, the phase controller ceases fine-grained phase adjustments and instead directs the adjustable oscillator to maintain only frequency lock with the receiver-side clock, typically at a reduced clock frequency. To prevent data corruption during this phase-unlocked state, the computational circuitry dynamically inserts asynchronous FIFO buffers (Clock Domain Crossing circuits) between the deserializer output and the main processing path, and between the processing path and the serializer input. These FIFOs introduce additional latency but guarantee data integrity by absorbing phase differences. Concurrently, the adjustable oscillator is reconfigured to consume minimal power (e.g., by reducing VCO bias or operating with slower, less precise components). The system provides a "Limited Functionality" signal to external systems, indicating reduced performance but continued, albeit slower, operation.

stateDiagram-v2
    [*] --> Initializing
    Initializing --> NormalOperation : System Ready & Phase Locked
    NormalOperation --> LowPowerMode : Low Power Command OR High Threshold Phase Error
    NormalOperation --> SafeMode : Critical Phase Error (No Lock)

    state NormalOperation {
        RX_CLK --> PhaseDetector
        TX_CLK_Interim --> PhaseDetector
        PhaseDetector --> PhaseController : Phase Diff
        PhaseController --> AdjustableOscillator : Phase Adjust
        AdjustableOscillator --> Serializer : Wire Rate CLK
        ComputationalLogic --> Serializer : Data
    }

    state LowPowerMode {
        RX_CLK --> FrequencyLockedOscillator : Freq Ref
        FrequencyLockedOscillator --> Serializer : Low Power WR_CLK
        Deserializer --> AsyncFIFO_RX : Data In
        AsyncFIFO_RX --> ComputationalLogic : Data Out
        ComputationalLogic --> AsyncFIFO_TX : Data In
        AsyncFIFO_TX --> Serializer : Data Out
        note on LowPowerMode
            Phase alignment is relaxed.
            Focus on frequency lock.
            Increased latency via Async FIFOs.
            Reduced power consumption.
        end note
    }

    state SafeMode {
        RX_CLK --> FrequencyLockedOscillator : Freq Ref
        FrequencyLockedOscillator --> Serializer : Safe WR_CLK
        Deserializer --> AsyncFIFO_RX_Crit : Data In
        AsyncFIFO_RX_Crit --> ComputationalLogic : Data Out
        ComputationalLogic --> AsyncFIFO_TX_Crit : Data In
        AsyncFIFO_TX_Crit --> Serializer : Data Out
        note on SafeMode
            Emergency mode, data integrity prioritized.
            Possibly further reduced clock speed.
            System attempts to re-establish NormalOperation.
        end note
    }

    LowPowerMode --> NormalOperation : Optimal Phase Re-established
    SafeMode --> NormalOperation : Optimal Phase Re-established
    SafeMode --> Shutdown : Unrecoverable Error
    LowPowerMode --> Shutdown : External Shutdown Command

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Combination Prior Art Scenarios

These scenarios combine the teachings of US10771069 with existing open-source standards, demonstrating how the patent's core concepts could be rendered obvious in various system contexts.

1. FPGA with Internal PLL for Synchronous Ethernet (SyncE) on O-RAN Fronthaul:

   • Description: An FPGA system as described in US10771069 (Claims 1, 25, 38, 59, 75, 96) is used as a Radio Unit (RU) or Distributed Unit (DU) in an Open Radio Access Network (O-RAN) fronthaul interface. The first serial data stream comprises Common Public Radio Interface (CPRI) or enhanced CPRI (eCPRI) data, and the second serial data stream is the processed CPRI/eCPRI data. The first clock signal is a recovered clock from the incoming CPRI/eCPRI stream, which often carries timing information. The core idea of internally aligning the receiver-side clock (derived from the CPRI/eCPRI data) and the transmitter-side clock (for outgoing CPRI/eCPRI) to eliminate clock domain crossings within the FPGA is applied.
   • Combination Prior Art: The O-RAN Alliance specifications (e.g., O-RAN Fronthaul Specifications, WG4, specifically relating to timing and synchronization over Ethernet, which leverages IEEE 1588 Precision Time Protocol (PTP) and Synchronous Ethernet (SyncE) as defined in IEEE 802.3 and IEEE 1588). A person skilled in the art, familiar with the need for precise timing in radio access networks and the principles of SyncE/PTP, would find it obvious to apply the internal FPGA phase alignment techniques of US10771069 to minimize latency and ensure phase coherence for CPRI/eCPRI processing within an O-RAN RU or DU, particularly given the known challenges of clock synchronization in these environments. The internal PLL in the FPGA would be used to align the transmit clock to the recovered receive clock, eliminating the need for traditional clock domain crossing logic for optimal latency in real-time radio signal processing.

2. FPGA with Internal PLL for High-Performance Computing (HPC) Interconnect using OpenCAPI/Gen-Z:

   • Description: The FPGA system of US10771069 is employed as a network interface card (NIC) or a custom accelerator in an HPC environment. The first serial data stream and second serial data stream are high-speed data packets transmitted over a peer-to-peer interconnect fabric adhering to OpenCAPI or Gen-Z specifications. The first clock signal is the recovered data clock from the incoming OpenCAPI/Gen-Z link, and the second clock signal is a system reference clock. The FPGA's internal phase detector and phase controller adjust an on-chip PLL to synchronize the transmitter-side clock precisely with the receiver-side clock, minimizing latency for data transfer between compute nodes or between CPU/GPU and FPGA accelerators over the OpenCAPI/Gen-Z fabric. This prevents unnecessary buffer latencies that would otherwise accumulate due to clock domain mismatches in high-bandwidth, low-latency applications.
   • Combination Prior Art: The OpenCAPI (Coherent Accelerator Processor Interface) and Gen-Z standards, both open standards for high-speed, low-latency memory-semantic fabrics. These standards inherently address high-speed data transfer and synchronization challenges. An engineer designing an OpenCAPI or Gen-Z compliant FPGA interface, needing to minimize transaction latency, would readily combine the teachings of US10771069 to achieve efficient internal clock synchronization within the FPGA, thereby optimizing performance for memory-semantic operations and coherency protocols.

3. FPGA with Internal PLL for Real-time Control Systems using EtherCAT/PROFINET:

   • Description: The FPGA system as described in US10771069 is used in an industrial automation context as a master or slave device for real-time control, communicating over an EtherCAT or PROFINET network. The first serial data stream consists of incoming process data or control commands from the industrial network, and the second serial data stream comprises outgoing sensor readings or actuator commands. The first clock signal is derived from the highly deterministic EtherCAT/PROFINET synchronization mechanism (e.g., distributed clocks in EtherCAT). The FPGA's internal phase alignment ensures that computational circuitry processing the incoming data and preparing outgoing data operates without significant clock domain crossing delays, maintaining the strict cycle times and jitter requirements of these real-time protocols. The phase controller and adjustable oscillator actively match the internal transmit clock to the network-derived receive clock.
   • Combination Prior Art: The EtherCAT (Ethernet for Control Automation Technology) and PROFINET (Process Field Network) standards, which are open Ethernet-based protocols widely used in industrial automation for real-time communication. These protocols feature precise synchronization mechanisms and strict timing requirements. A control engineer tasked with implementing an EtherCAT/PROFINET node on an FPGA, and aware of the need to eliminate latency in data processing paths for deterministic operation, would find it obvious to apply the internal phase-locked loop and phase alignment techniques of US10771069 to achieve optimal performance and compliance with the stringent timing specifications of these industrial real-time networks.