Obviousness

The obviousness analysis under 35 U.S.C. § 103 requires determining whether the differences between the claimed invention and the prior art would have been obvious to a person having ordinary skill in the art (PHOSITA) at the time of the invention. This involves considering the scope and content of the prior art, the differences between the claimed invention and the prior art, and the level of ordinary skill in the pertinent art. A motivation to combine prior art references must exist, which can come from the knowledge of those skilled in the art, from the prior art references themselves, or from the nature of the problem to be solved.

Level of Ordinary Skill in the Art (PHOSITA):
A PHOSITA in this field would likely possess a graduate degree (Master's or Ph.D.) in electrical engineering, materials science, or a related discipline, with several years of experience in semiconductor device fabrication, optoelectronics, or integrated circuit design, particularly with expertise in photodetectors, avalanche photodiodes, and silicon photonics. This individual would be familiar with various etching techniques, epitaxial growth of silicon and germanium-silicon alloys, and the integration of optical devices with CMOS/BiCMOS electronics.

Motivation to Combine:
The primary motivation for combining elements from the prior art to arrive at the claimed invention would be to improve the performance of photosensitive devices, specifically focusing on enhanced light absorption, increased quantum efficiency, higher data rates, and monolithic integration with existing silicon electronics for cost reduction and efficiency in applications like fiber-optic communication, data centers, and LIDAR. The art clearly recognized the trade-offs between efficiency, speed, and cost in photodetectors and sought solutions to overcome these limitations.

Combinations of Prior Art for Obviousness:

1. Claims 1, 16, and 25 (General Microstructure-Enhanced Photodetector with Integration)

• References: US9525084B2 (W&wsens Devices Inc.), Mavrokefalos et al. (2012), Singh et al. (2011)

• Discussion: US9525084B2, a patent within the same family as US10446700, broadly describes techniques for enhancing photon absorption in semiconductors using microstructures like holes to increase quantum efficiency and bandwidth for silicon photodiodes and avalanche photodiodes. It explicitly mentions the integration of such devices on the same Si chip with CMOS, BiCMOS, and other electronics. Mavrokefalos et al. (2012) teach the use of inverted nanopyramid light-trapping schemes in thin crystalline silicon films to significantly enhance light absorption for solar cell applications, noting that these structures can be fabricated at wafer scale via a low-cost wet etching process. This reference demonstrates the effectiveness of microstructures, specifically inverted pyramids, for light trapping and absorption enhancement in silicon, a core element of US10446700. Singh et al. (2011) provide a review of Silicon-On-Insulator (SOI) technology, highlighting its advantages for reducing power consumption, increasing speed, and enabling higher integration density in CMOS ICs by using a thin silicon layer on top of a buried oxide.

• Motivation to Combine: A PHOSITA, aware of the general benefits of microstructures for light absorption (US9525084B2, Mavrokefalos et al.) and the advantages of SOI technology for high-performance and integrated electronics (Singh et al.), would have been motivated to combine these concepts to create a microstructure-enhanced photodetector on an SOI substrate. The motivation would be to leverage the improved light-trapping capabilities of microstructures, as demonstrated by Mavrokefalos et al., with the established benefits of SOI technology for monolithic integration with high-speed CMOS/BiCMOS circuits, as broadly disclosed in US9525084B2. The goal would be to achieve higher quantum efficiency and faster operation in a compact, integrated device, addressing the known challenges in high-speed optical communication. The general concept of integrating photodetectors with microstructures and electronic circuits on a single chip is already present in the prior art, including US9525084B2.

2. Claims 1, 16, and 25 (Specific Etching Techniques and Hole Shapes)

• References: US9525084B2, Fan et al. (2013), Mavrokefalos et al. (2012)

• Discussion: US9525084B2 mentions that microstructures like holes effectively increase photon absorption and that these holes can be formed by etching. Fan et al. (2013) discuss the differences in etching characteristics of TMAH and KOH for preparing inverted pyramids for silicon solar cells, detailing how these etchants can create specific hole shapes. Mavrokefalos et al. (2012) specifically demonstrate efficient light trapping using inverted nanopyramid structures fabricated via a low-cost wet etching process. US10446700 mentions that the microstructure holes can be etched using KOH solution and also refers to Fan et al. and Mavrokefalos et al. for inverted pyramids. The patent further explicitly states that the holes can be shaped as inverted pyramids and have triangular sections.

• Motivation to Combine: A PHOSITA seeking to implement the microstructure-enhanced absorption described in US9525084B2 would naturally look to known etching techniques for forming such structures. Fan et al. and Mavrokefalos et al. directly provide the methodology for creating inverted pyramid-shaped holes in silicon using wet etching (KOH or TMAH), which are shown to be effective for light trapping and absorption enhancement. The motivation to combine would be to utilize these known and effective etching processes to fabricate the microstructure holes described in US9525084B2, achieving the desired light-trapping geometry (e.g., inverted pyramids) for improved quantum efficiency in photodetectors. The patent itself cites these references for the etching of inverted pyramids.

3. Claim 1 (GeSi Alloys and Monolithic Integration)

• References: US9525084B2, Montalenti et al. (2014) , US20180102442A1 (which is US10446700's own publication history)

• Discussion: US9525084B2 states that the photodetector can comprise a germanium-based photon absorbing layer formed by epitaxial growth above silicon layers, and that the photodetector can be an avalanche photodiode with a multiplication region formed of silicon. US10446700 also discusses the use of GeₓSi₁₋ₓ alloys for the intermediate (I) layer, where x is greater than zero, to extend the detectable wavelength range and mentions that strain in the GeSi alloy can narrow the bandgap. Montalenti et al. (2014) discuss the fully coherent growth of Ge on free-standing Si(001) nanomesas, indicating the knowledge of growing GeSi materials on silicon with controlled strain. The patent explicitly refers to Montalenti et al. regarding the growth of GeSi alloy and/or Ge within nano/microstructured holes.

• Motivation to Combine: Given the stated goal of extending the detectable wavelength range beyond silicon's intrinsic limits, a PHOSITA would be motivated to incorporate germanium or GeSi alloys into the absorbing layer, as suggested by US9525084B2. The knowledge from Montalenti et al. (2014) regarding the controlled growth of strained GeSi on silicon provides a clear method for achieving such a material system. Combining the microstructure-enhanced absorption concept from US9525084B2 with the epitaxial growth techniques for GeSi alloys, a PHOSITA would find it obvious to create a photodetector using GeSi in the intermediate layer within microstructure holes to enable detection at longer wavelengths while maintaining enhanced absorption, as indicated by the patent's own description.

4. Claims 1 and 16 (Dielectric Material in Propagation Path)

• References: US9525084B2, Paneva et al. (1995), US6222257B1

• Discussion: US10446700 claims a layer of dielectric material in the propagation path of the optical input, covering the holes and spaces between them. US9525084B2, in describing microstructures, is silent on the specific material filling or covering the holes, but it is implied that the microstructure itself is a light-trapping feature. Prior art references such as Paneva et al. (1995) and US6222257B1 discuss the use of silicon nitride and silicon dioxide as etch stop layers in silicon processing. These materials are well-known dielectrics in semiconductor manufacturing.

• Motivation to Combine: A PHOSITA would be motivated to incorporate a dielectric material, such as silicon dioxide or nitride, over the microstructure holes and spaces. This would serve multiple purposes: protecting the etched structures, providing mechanical stability, and potentially acting as an anti-reflection coating or waveguide cladding to further enhance light coupling into the device. The use of common dielectrics in semiconductor manufacturing for passivation and optical purposes would be well within the knowledge of a PHOSITA and would be a logical step to improve the robustness and optical performance of the microstructure-enhanced photodetector described in US9525084B2.

5. Claim 25 (Method of Making with Air-Filled Volume)

• References: US9525084B2, Singh et al. (2011), Wu et al. (cited in US10446700 description for DRIE, ICP, HAR etching)

• Discussion: US10446700 describes forming an air-filled volume between the substrate and the MSPD. The patent also refers to forming holes using wet and dry etching techniques like DRIE, ICP, and HAR etching. US9525084B2 discusses the formation of microstructure holes by etching. Singh et al. (2011) describe SOI manufacturing methods, including the use of buried oxide layers to provide dielectric isolation. While not explicitly teaching "air-filled volume" in the context of light trapping, SOI technology inherently involves a buried dielectric layer, which could be selectively removed or patterned to create voids. The concept of creating voids or air gaps in silicon structures for various purposes, including optical applications, was known in the art (e.g., photonic crystals).

• Motivation to Combine: A PHOSITA would be motivated to create air-filled volumes beneath the photodetector, particularly if working with SOI wafers. Air gaps can serve as effective reflectors or provide optical isolation, further enhancing light trapping within the active region of the photodetector by total internal reflection, as noted within US10446700 itself regarding bottom holes. The combination of etching techniques (like DRIE mentioned in US10446700, and as implicitly taught by other prior art for micro-machining silicon) with SOI wafers to create controlled air gaps or voids for optical enhancement would be an obvious design choice for improving the efficiency of the microstructure-enhanced photodetectors.

6. Claim 1 (Integration with Active Electronic Circuit)

• References: US9525084B2, Zhang et al. (2017), Singh et al. (2011)

• Discussion: Claim 1 of US10446700 describes a single-chip device comprising an integrated combination of an MSPD and an active electronic circuit, both formed on or in a single substrate. US9525084B2 explicitly states that its microstructure-enhanced devices "can be conveniently integrated on the same Si chip with CMOS, BiCMOS, and other electronics, with resulting packaging benefits and reduced capacitance and thus higher speeds." Zhang et al. (2017) demonstrate a CMOS-compatible, nanostructured, thin-junction Si single-photon avalanche diode that breaks the trade-off between photon detection efficiency and timing jitter, noting its "complementary metal oxide semiconductor compatibility" and that the result "provides a practical and complementary metal oxide semiconductor compatible method to improve the performance of single-photon avalanche detectors, image sensor arrays, and silicon photomultipliers over a broad spectral range." Singh et al. (2011) discusses SOI technology as important for leading-edge CMOS IC production and system-on-chip (SOC) applications.

• Motivation to Combine: The explicit teaching in US9525084B2 of integrating microstructure-enhanced photodetectors with CMOS/BiCMOS electronics on a single chip provides a direct motivation for this combination. Zhang et al. further reinforce the feasibility and benefits of CMOS-compatible nanostructured devices, addressing performance trade-offs critical for high-speed applications. Singh et al. highlight SOI as a key technology for advanced CMOS integration. A PHOSITA would have been highly motivated to combine these known elements to create a fully integrated, high-performance optical receiver on a single silicon chip, driven by the desire for reduced cost, smaller footprint, and improved electrical characteristics (e.g., lower capacitance and higher speed) in high-volume applications like data centers and telecommunications.