Obviousness

Obviousness Analysis under 35 U.S.C. § 103 for US Patent 8253180

The obviousness analysis under 35 U.S.C. § 103 requires determining whether the differences between the claimed invention and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art (PHOSITA). This often involves identifying a motivation to combine existing prior art references to arrive at the claimed invention with a reasonable expectation of success.

The present patent, US 8253180, addresses issues in MISFETs using high dielectric constant (high-k) gate insulating films. The key inventive concepts revolve around the continuity and varied thickness of the high-k gate insulating film underneath the gate electrode and adjacent sidewalls.

Prior Art References:

The patent explicitly references the following prior art:

1. Watanabe (2005): "Ken Watanabe, HfSiON - CMOS technology for achieving high performance and high reliability, Semi. Forum Japan, 2005". This reference teaches "known MISFETs using a high dielectric constant gate insulating film" as illustrated in FIGS. 16A and 16B of US 8253180. [cite: The full patent text, "FIGS. 16A and 16B are cross-sectional views illustrating respective structures of known MISFETs using a high dielectric constant gate insulating film, respectively (see Ken Watanabe, HfSiON - CMOS technology for achieving high performance and high reliability, Semi. Forum Japan, 2005)."]
   • FIG. 16A depicts a basic MISFET with a gate electrode 105, a high dielectric constant gate insulating film 104 beneath it, and an insulating sidewall 107. [cite: The full patent text, "As shown in FIG. 16A , a gate electrode 105 is formed on a region of a well 102 surrounded by a STI (shallow trench isolation) 103 . The gate electrode 105 is provided on the region with a high dielectric constant gate insulating film 104 interposed therebetween. An insulating sidewall 107 is formed on each side of the gate electrode 105 ."]
   • FIG. 16B introduces an insulating offset sidewall 106 positioned between the gate electrode 105 and the main sidewall 107. [cite: The full patent text, "A structure shown in FIG. 16B is different from a structure shown in FIG. 16A in that a sidewall 107 is formed on each side of a gate electrode 105 with an insulating offset sidewall 106 interposed therebetween."]
2. Sayama (2000): "H. Sayama et al., IEDM Tech. Dig., 2000, p. 239". This reference describes a "double sidewall type MISFET in which an overlapping amount between a gate electrode and an extension region can be optimized in a simple manner." [cite: The full patent text, "a double sidewall type MISFET (see H. Sayama et al., IEDM Tech. Dig., 2000, p. 239) in which an overlapping amount between a gate electrode and an extension region can be optimized in a simple manner will be described in the second embodiment."]

Obviousness of Independent Claims:

Independent Claim 1: Semiconductor Device with Continuous, Thinned High-k Film

Independent Claim 1 describes a semiconductor device with a high dielectric constant gate insulating film that is continuously formed from under the gate electrode to under the insulating sidewall, and at least the part under the insulating sidewall has a smaller thickness than the part under the gate electrode. [cite: Independent Claim 1]

Combination of Prior Art: Watanabe (2005) + General Knowledge in Semiconductor Processing

Rationale for Obviousness:

1. Known Elements from Watanabe: Watanabe (FIG. 16A) already teaches the basic structure of a MISFET comprising a high dielectric constant gate insulating film, a gate electrode formed thereon, and insulating sidewalls on the side surfaces of the gate electrode. [cite: The full patent text, "As shown in FIG. 16A , a gate electrode 105 is formed on a region of a well 102 surrounded by a STI (shallow trench isolation) 103 . The gate electrode 105 is provided on the region with a high dielectric constant gate insulating film 104 interposed therebetween. An insulating sidewall 107 is formed on each side of the gate electrode 105 ."]

2. Motivation to make High-k Film Continuous: The present patent itself highlights a critical problem with "known MISFETs using a high dielectric constant gate insulating film": "side end portions of the high dielectric constant gate insulating film are in direct contact with sidewalls. Thus, in forming sidewalls of, for example, a silicon oxide film or the like, a composition of the side end portions of the high dielectric constant gate insulating film becomes closer to SiO2 or like other inconvenience occurs. As a result, reduction in the dielectric constant and insulation property of the high dielectric constant gate insulating film is caused at gate electrode end part, so that device characteristics of the MISFET are deteriorated and the reliability of the gate insulating film is degraded." [cite: The full patent text confirms this statement.]
   A PHOSITA, recognizing this degradation issue at the interface between the high-k gate insulating film and the sidewall in the Watanabe structure, would be motivated to extend the high-k film continuously under the insulating sidewall to prevent direct contact and preserve the film's dielectric and insulating properties. Protecting critical layers by extending them under subsequent structures is a common design practice in semiconductor manufacturing.

3. Motivation to Reduce Thickness of the Extended High-k Film: If a PHOSITA were to extend the high-k gate insulating film under the sidewall (as motivated above), they would immediately encounter two further problems, which the patent also explicitly identifies:

   • Increased Parasitic Capacitance: The patent states that "when the high dielectric constant gate insulating film is kept remaining under the sidewalls, a capacitance between gate/drain regions is increased, thus resulting in adverse effects on circuit speed." [cite: The full patent text confirms this statement.] A PHOSITA knows that capacitance is inversely proportional to the dielectric thickness. Therefore, to mitigate this increased gate-to-drain capacitance, a PHOSITA would be motivated to reduce the thickness of the high-k film in the region under the sidewall, which overlaps with the extension/drain regions, thereby maintaining circuit speed.
   • Difficulty in Forming Shallow Junctions: The patent notes, "when extension implantation or LDD (lightly doped drain) implantation is performed, it is necessary to implant ions through a high dielectric constant film. Thus, when ion implantation is performed, expansion of an implanted impurity in the depth direction is increased... so that desired device characteristics can not be obtained." [cite: The full patent text confirms this statement.] This problem is exacerbated by the inherent properties of high-k films, including their thickness and heavy metal content, which result in a small projection range (Rp) for implanted ions, requiring higher acceleration energy. [cite: The full patent text, "Reason 1) With use of a high dielectric constant film as a gate insulating film, a desired dielectric constant can be achieved even without having the thickness of the high dielectric constant film reduced. Therefore, the thickness of the high dielectric constant film has to be set at a large value. Reason 2) A high dielectric constant film contains heavy metal and Rp (projection range) of implanted ions is small."] To overcome these challenges and enable the formation of shallow junctions for extension or LDD regions, a PHOSITA would be motivated to reduce the thickness of the high-k film in these areas to lower the required ion implantation energy and achieve better control over doping profiles. This is a direct and predictable solution based on the physics of ion implantation through thin films.

Therefore, a PHOSITA, starting from the known structure of Watanabe and confronted with the recognized problems of high-k gate dielectrics, would have been motivated to first extend the high-k film for protection and then thin it in the sidewall region to optimize electrical performance and doping profiles.

Independent Claim 6: Method for Fabricating with Etching Step

Independent Claim 6 describes a method including the steps of forming a high dielectric constant gate insulating film, forming a gate electrode, then etching the part of the high dielectric constant gate insulating film external to the gate electrode to reduce its thickness, and finally forming an insulating sidewall. [cite: Independent Claim 6]

Combination of Prior Art: Watanabe (2005) + General Knowledge in Semiconductor Processing

Rationale for Obviousness:

1. Standard Fabrication Steps: Steps a), b), and d) (forming high-k film, gate electrode, and sidewall) are standard in MISFET fabrication, exemplified by Watanabe. [cite: The full patent text, "FIGS. 11A through 11F are cross-sectional views illustrating respective steps for fabricating a semiconductor device according to the fifth embodiment of the present invention."]
2. Motivation for Etching (Step c): The motivation for reducing the thickness of the high-k film (as taught in step c) is identical to the motivations discussed for Claim 1: to reduce parasitic capacitance and facilitate shallow ion implantation for extension/LDD regions. [cite: The full patent text, "the part of the high dielectric constant gate insulating film 4 located in the external side to the gate electrode 5 has a reduced thickness, so that increase in acceleration energy can be suppressed. Accordingly, a shallow junction can be formed in the n-type extension region 10 in a simple manner and thus device characteristics can be improved in a simple manner."]
3. Timing and Technique of Etching: Performing the selective etching after gate electrode formation (which defines the lateral extent of the gate and thus the regions where the high-k film should be thinned) and before sidewall formation (which would then be built upon the thinned film or would mask further etching) is a logical and routine sequencing for a PHOSITA. Standard selective etching techniques (e.g., wet etching using hydrofluoric acid or selective dry etching) are well-known and routinely applied for modifying dielectric film thicknesses in specific areas. [cite: The full patent text, "part of the high dielectric constant gate insulating film 4 located in the external side to the gate electrode 5 is removed by a thickness of about 2 nm by selective etching."]

Thus, the method claimed in Claim 6 would be an obvious process modification for a PHOSITA seeking to implement the structural benefits of Claim 1 using conventional semiconductor fabrication techniques.

Independent Claims 13-17: Semiconductor Devices with Multiple Sidewalls

These claims describe semiconductor devices featuring first and second insulating sidewalls, with variations in the continuity and thickness profile of the high dielectric constant gate insulating film relative to these sidewalls. [cite: Independent Claims 13, 14, 15, 16, 17]

Combination of Prior Art: Watanabe (2005) + Sayama (2000) + General Knowledge in Semiconductor Processing

Rationale for Obviousness:

1. Known Double Sidewall Structure: The use of multiple sidewalls (e.g., an offset sidewall and a main sidewall) in MISFETs to optimize gate-extension overlap is explicitly taught by Watanabe (FIG. 16B) [cite: The full patent text, "A structure shown in FIG. 16B is different from a structure shown in FIG. 16A in that a sidewall 107 is formed on each side of a gate electrode 105 with an insulating offset sidewall 106 interposed therebetween. Thus, an overlapping amount of the gate electrode 105 and an extension region 110 can be optimized in a simple manner."] and by Sayama (2000). [cite: The full patent text, "a double sidewall type MISFET (see H. Sayama et al., IEDM Tech. Dig., 2000, p. 239) in which an overlapping amount between a gate electrode and an extension region can be optimized in a simple manner will be described in the second embodiment."] Therefore, the fundamental concept of using a "first insulating sidewall" (offset) and a "second insulating sidewall" is firmly in the prior art.
2. Application of Obvious Modifications: The remaining features in Claims 13-17 involve the same principles of continuous and thickness-reduced high-k films as discussed for Claim 1, now applied to the known double sidewall configurations.
   • Motivation for Continuity and Reduced Thickness under First Sidewall (Claim 13): The motivations for extending the high-k film and reducing its thickness under the first (offset) sidewall are identical to those for Claim 1 (protection, reduced parasitic capacitance, facilitated shallow implantation). [cite: The full patent text confirms these motivations for the second embodiment, corresponding to Claim 13 structure.]
   • Motivation for Varying Thickness Profiles (Claims 14-17): The different thickness profiles described in Claims 14-17 (e.g., complete removal under the second sidewall, same thickness under both sidewalls, progressively thinner under each sidewall) represent routine optimization efforts for a PHOSITA. These variations directly address the balance between minimizing parasitic capacitance, controlling short channel effects, and optimizing doping profiles. For example, Claim 14's feature of the high-k film not being under the second insulating sidewall is explicitly described in the patent as a means to "further suppress" parasitic capacitance, demonstrating a known technical goal and a direct way to achieve it. [cite: The full patent text, "Moreover, according to this embodiment, the high dielectric constant gate insulating film 4 B does not exist under the sidewall 7 . Thus, increase in a capacitance between the gate electrode 5 and each of the n-type source/ drain regions 12 can be further suppressed so that a small capacitance can be maintained. Accordingly, increase in a parasitic capacitance and adverse effects on circuit speed due to the increase can be suppressed at a minimum level."] A PHOSITA would routinely explore such variations using conventional and predictable fabrication steps.

Reasonable Expectation of Success:

For all independent claims, the proposed modifications involve standard semiconductor processing techniques, including etching, deposition, and ion implantation. The effects of altering dielectric thickness on capacitance and ion penetration are well-understood and predictable in the art. Therefore, a PHOSITA would have a reasonable expectation of success in combining the teachings of Watanabe and Sayama with general knowledge to arrive at the claimed inventions.

Conclusion:

Based on the analysis, the independent claims of US Patent 8253180 are likely obvious under 35 U.S.C. § 103. The problems addressed by the patent (high-k film degradation, increased parasitic capacitance, and challenges in shallow junction formation) were known or would be immediately apparent to a PHOSITA working with high-k dielectrics. The proposed solutions—extending the high-k film for protection and selectively thinning it under the sidewalls—are direct and predictable modifications using conventional semiconductor fabrication techniques. The variations in thickness profiles for multiple sidewall structures represent routine optimization efforts within the scope of a PHOSITA.