Prior art

To identify the most relevant prior art for US Patent 7844882, I will examine the patents cited during its prosecution. The "Citations" section of US7844882 lists twelve references. However, US20060088054A1 and US20090300450A1 appear to be earlier publications or continuations of the same inventive family as US7844882, or later applications that cite US7844882, and thus are not considered anticipatory prior art under 35 U.S.C. § 102. Therefore, the analysis will focus on the remaining ten cited patents.

The core innovative aspects of US7844882, as described in its claims, involve sharing memory and processing power between multiple interleaver/deinterleaver modules in a telecommunications transceiver. This sharing is dynamically allocated based on application requirements (e.g., data rate, latency, bit error rate, impulse noise protection) and involves the exchange of configuration messages between transceivers.

Here's an analysis of the potentially anticipatory prior art:

1. US6337877B1

• Full Citation: US6337877B1, "Method and apparatus for scaling modem transfer capacity in a multi-channel communications system," filed August 27, 1998, published January 8, 2002.
• Assignee: Legerity, Inc.
• Brief Description: This patent describes a multi-channel communications system that scales modem transfer capacity, allowing modems to dynamically switch between different operational modes to support various data rates and channel conditions. It focuses on allocating channel resources (e.g., tone sets) dynamically.
• Potential Anticipation (35 U.S.C. § 102): While US6337877B1 deals with dynamic resource allocation in a multi-channel modem, its focus is on scaling modem transfer capacity and channel resources (like tone sets). It does not explicitly disclose the sharing of a single physical memory between interleavers and deinterleavers, nor the allocation of bytes of memory to specific interleavers/deinterleavers based on performance requirements, as claimed in US7844882 (e.g., claim 1, "allocating... a first number of bytes of the shared memory to the interleaver"). Therefore, it is unlikely to directly anticipate claims 1-16.

2. EP1225735A1

• Full Citation: EP1225735A1, "Data communication system," filed July 7, 2000, published July 24, 2002.
• Assignee: Matsushita Electric Industrial Co., Ltd.
• Brief Description: This patent describes a data communication system that manages buffer memory for retransmission control in a packet communication system. It aims to reduce required buffer memory by appropriately setting the maximum buffer capacity based on factors like data transfer rate and round trip time.
• Potential Anticipation (35 U.S.C. § 102): EP1225735A1 addresses buffer memory management for retransmission, considering data rates. This touches upon the general concept of managing memory based on communication parameters. However, it specifically concerns retransmission buffers and does not explicitly detail shared memory for interleavers and deinterleavers that are simultaneously used, nor does it describe transmitting messages during initialization to specify maximum interleaver memory, as detailed in US7844882's claims. It might broadly overlap with the concept of memory management based on data rates, but lacks the specificity of interleaver/deinterleaver shared memory allocation. It could potentially anticipate the broad concept of managing memory based on communication parameters, but not the specific architecture for interleavers/deinterleavers.

3. EP1246409A1

• Full Citation: EP1246409A1, "Packet retransmission system, packet transmission device, packet reception device, packet retransmission method, packet transmission method and packet reception method," filed October 5, 2000, published October 2, 2002.
• Assignee: Mitsubishi Denki Kabushiki Kaisha
• Brief Description: This patent describes a packet retransmission system using buffer memories for storing packets, where the buffer memory usage is managed based on a priority control unit for efficient retransmission.
• Potential Anticipation (35 U.S.C. § 102): Similar to EP1225735A1, this patent focuses on buffer management for packet retransmission with priority control. It does not disclose the unique aspects of shared memory specifically for interleavers and deinterleavers, their simultaneous use, or the transmission of memory capability messages during initialization, as claimed in US7844882.

4. US20030067877A1

• Full Citation: US20030067877A1, "Communication system and techniques for transmission from source to destination," filed September 27, 2001, published April 10, 2003.
• Assignee: Raghupathy Sivakumar
• Brief Description: This application describes a communication system that dynamically adapts data transmission rates and paths based on channel conditions and user requirements. It can use multiple paths with different characteristics for different types of data.
• Potential Anticipation (35 U.S.C. § 102): This application broadly covers dynamic adaptation of data transmission based on requirements and the use of multiple paths. This aligns with the context of US7844882 (multiple latency paths for different applications). However, it does not explicitly detail the sharing of a single memory block between interleavers and deinterleavers, nor the specific allocation of memory bytes to them, as described in US7844882's claims. It establishes the general problem domain but not the specific solution.

5. WO2003063060A2

• Full Citation: WO2003063060A2, "Asymmetric digital subscriber line modem apparatus and methods therefor," filed January 24, 2002, published July 31, 2003.
• Assignee: Broadcom Corporation
• Brief Description: This patent describes an ADSL modem and methods for its operation, including aspects of data processing, framing, and handling multiple data paths. It relates to the implementation of DSL systems.
• Potential Anticipation (35 U.S.C. § 102): This is a general patent for ADSL modems, which would inherently include framers, coders, and interleavers. While it likely deals with managing resources in such a system, the abstract does not indicate a specific disclosure of shared memory for multiple interleavers/deinterleavers with dynamic allocation based on communication parameters and inter-transceiver messaging, which are key to US7844882's claims. Without delving deeper into its claims and detailed description, it's hard to assess specific anticipation, but the abstract suggests a broader scope.

6. US6707822B1

• Full Citation: US6707822B1, "Multi-session asymmetric digital subscriber line buffering and scheduling apparatus and method," filed January 7, 2000, published March 16, 2004.
• Assignee: Agere Systems Inc.
• Brief Description: This patent describes an ADSL buffering and scheduling system for supporting multiple concurrent data sessions with different quality-of-service (QoS) requirements. It uses buffering for managing data flow and latency.
• Potential Anticipation (35 U.S.C. § 102): US6707822B1 addresses buffering and scheduling for multiple sessions with varying QoS requirements, which is a related problem to US7844882's objective of supporting multiple applications with different requirements. However, its focus is on general buffering and scheduling rather than the specific sharing of a single physical interleaver/deinterleaver memory and its byte-level allocation based on inter-transceiver negotiation, as claimed in US7844882 (e.g., claims 1 and 5).

7. US20040114536A1

• Full Citation: US20040114536A1, "Method for communicating information on fast and slow paths," filed October 16, 2002, published June 17, 2004.
• Assignee: O'rourke Aidan
• Brief Description: This application describes a method for communicating information using fast and slow paths in a DSL system, where the choice of path (and associated FEC/interleaving) depends on the data type and QoS requirements. It relates to the different latency paths used in DSL.
• Potential Anticipation (35 U.S.C. § 102): This patent directly deals with the concept of fast and slow paths and their corresponding FEC and interleaving settings, which is a foundational concept also present in US7844882. US7844882 explicitly refers to "latency paths" (which are FCI blocks), linking directly to this concept. While US20040114536A1 discusses FEC/interleaving settings for these paths, it does not explicitly detail the sharing of a single memory across multiple interleavers/deinterleavers, the allocation of portions of that shared memory (in bytes) to them, or the signaling of maximum memory capabilities between transceivers for this shared resource, as described in US7844882's claims (e.g., claim 1 specifies transmitting a message during initialization specifying a maximum number of bytes of memory available to be allocated to an interleaver within a shared memory). This patent could provide strong background for the "latency path" concept, but likely does not fully anticipate the shared memory mechanism.

8. US6775320B1

• Full Citation: US6775320B1, "Method and a multi-carrier transceiver supporting dynamic switching between active application sets," filed March 12, 1999, published August 10, 2004.
• Assignee: Aware, Inc.
• Brief Description: This patent, from the same original assignee as US7844882, describes a multi-carrier transceiver that supports dynamic switching between different application sets. It discusses allocating resources (like bits, power, latency paths) to different applications to meet their QoS requirements. It is explicitly cited in US7844882's background as describing "DSL systems supporting multiple applications and multiple framer/coder/interleaver FCI blocks (an FCI block is also referred to as a latency path)".
• Potential Anticipation (35 U.S.C. § 102): Given it's from the same assignee and explicitly referenced as background, US6775320B1 is highly relevant. It introduces the concept of multiple latency paths (FCI blocks) for different applications with varying QoS. This patent likely anticipates the general idea of supporting multiple latency paths and dynamically allocating resources to them. However, US7844882's novel contribution builds upon this by introducing the sharing of a single physical memory and processing module among these latency paths' interleavers/deinterleavers and coders/decoders, along with the inter-transceiver negotiation of memory capabilities for this shared resource. US6775320B1 focuses on allocating resources between paths, not necessarily sharing a single pool of memory across the interleaver/deinterleaver components of different paths simultaneously. It might anticipate the "plurality of modules" (latency paths) but not the "shared memory designed to be allocated to a plurality of the modules" as explicitly claimed in US7844882 (e.g., claim 1).

9. US6778589B1

• Full Citation: US6778589B1, "Symbol synchronous device and frequency hopping receiver," filed October 9, 1998, published August 17, 2004.
• Assignee: Futaba Denshi Kogyo Kabushiki Kaisha
• Brief Description: This patent describes a symbol synchronous device and frequency hopping receiver, focusing on synchronization in communication systems.
• Potential Anticipation (35 U.S.C. § 102): The subject matter of this patent (symbol synchronization, frequency hopping receivers) appears largely unrelated to the shared memory and processing resource allocation for interleavers/deinterleavers in a DSL transceiver, as claimed in US7844882. It is unlikely to anticipate any of the claims.

10. US20050180323A1

• Full Citation: US20050180323A1, "System for transmitting high quality speech signals on a voice over Internet protocol network," filed February 12, 2004, published August 18, 2005.
• Assignee: Beightol Dean D.
• Brief Description: This application describes a system for transmitting high-quality speech signals over VoIP networks, focusing on minimizing delay and maintaining quality by prioritizing voice data and using efficient coding.
• Potential Anticipation (35 U.S.C. § 102): This application deals with optimizing speech transmission for QoS, which is a type of application US7844882 considers. It discusses minimizing delay and efficient coding. However, it does not explicitly disclose the mechanism of shared interleaver/deinterleaver memory, its allocation in bytes based on requirements, or the communication of memory capabilities between transceivers. It addresses the application layer problem, but not the specific hardware/memory sharing solution of US7844882's claims.

Summary of Most Relevant Prior Art:

Based on this analysis, the most relevant prior art appears to be US6775320B1. This patent, by the same assignee, lays the groundwork for supporting multiple latency paths (FCI blocks) with different application requirements, a fundamental concept on which US7844882 builds. While US6775320B1 does not explicitly disclose the shared physical memory pool for interleavers/deinterleavers and the specific inter-transceiver negotiation of memory capabilities as claimed in US7844882 (e.g., claims 1, 5, 9, 13), it establishes the context of managing resources for diverse applications in a multi-carrier transceiver. The novelty of US7844882 lies in the specific implementation of shared memory and its dynamic, negotiated allocation for interleaving and deinterleaving functions across these latency paths.

US20040114536A1 is also highly relevant as it discusses the use of fast and slow paths with associated FEC/interleaving, reinforcing the problem domain that US7844882 addresses.

Other patents like EP1225735A1 and US6707822B1 touch upon general buffer management and QoS-based allocation, but they lack the specific focus on shared interleaver/deinterleaver memory and the inter-transceiver communication of memory capabilities that defines the claims of US7844882.