Prior art — US Patent 7502958

The most relevant prior art for US patent 7502958 is identified from its "Citations" section. An anticipation analysis under 35 U.S.C. § 102 requires that every element of a claim be disclosed, either expressly or inherently, in a single prior art reference. Given the extensive list of citations, this analysis will focus on identifying explicit disclosures within the cited patents that directly match the independent claims of US7502958, particularly concerning firmware's role in coordinating lockstep recovery with an operating system and hot spare management for boot processors.

Below is an analysis of the cited prior art:

Most Relevant Prior Art for US7502958

1. US 2004/0006722 A1 (Patterson et al.)

Full Citation: US 2004/0006722 A1, "Method and Apparatus for Recovery from Loss of Lock Step," published January 8, 2004.
Assignee: Hewlett-Packard Development Company, L.P.
Priority Date: July 3, 2002.
Publication Date: January 8, 2004.
Brief Description: This patent application describes a method and apparatus for recovery from loss of lockstep in a computing system, where upon detection of LOL, the state of a "good" processor in a lockstep pair is saved to memory, and then both processors are reset and reinitialized. The saved state is then copied to both processors. [cite: US7502958 Description]
Potential Anticipation (35 U.S.C. § 102):
- This reference explicitly teaches recovering from loss of lockstep by resetting processors and restoring state. However, US7502958 highlights a limitation, noting that this prior art "makes the processors unavailable for an amount of time without the OS having any knowledge regarding this unavailability, and if the amount of time required for recovery is too long, the system may crash." [cite: US7502958 Description] Therefore, it does not explicitly disclose the key distinguishing features of US7502958's independent claims, which involve the firmware triggering an operating system to idle and then re-recognize the processors using standard OS methods (like ACPI).
- Thus, US20040006722A1 does not anticipate Claims 1, 13, 19, or 23 of US7502958 because it lacks the specific OS interaction steps (idling and re-recognizing by OS) coordinated by firmware.

2. US 6,334,185 B1 (Goodwin et al.)

Full Citation: US 6,334,185 B1, "Fault tolerant multiprocessor system having system firmware for recovering from processor failures and methods therefor," issued December 25, 2001.
Assignee: Hewlett-Packard Company
Priority Date: May 19, 2000.
Publication Date: December 25, 2001.
Brief Description: This patent describes a fault-tolerant multiprocessor system where system firmware is responsible for recovering from processor failures. It outlines methods for firmware to manage and recover from various processor issues.
Potential Anticipation (35 U.S.C. § 102):
- While this patent broadly describes firmware-based recovery from processor failures, it does not specifically disclose the detailed mechanism of "lockstep protection" with master/slave processors, nor the explicit interaction with an operating system to "idle" and "re-recognize" processors using standard interfaces (e.g., ACPI) as taught in US7502958. Its description of recovery is more general.
- Therefore, US6334185B1 does not anticipate Claims 1, 13, 19, or 23 of US7502958 as it lacks the specific combination of lockstep processing, firmware determining recoverability based on lockstep mismatch, and the precise OS interaction for idling and reintroduction.

3. US 6,862,703 B1 (Jambulingam et al.)

Full Citation: US 6,862,703 B1, "Fault-tolerant processor system with redundant processing units and methods for re-synchronization thereof," issued March 1, 2005.
Assignee: Intel Corporation
Priority Date: February 24, 2003.
Publication Date: March 1, 2005.
Brief Description: This patent describes a fault-tolerant processor system utilizing redundant processing units (e.g., in lockstep) and methods for re-synchronizing these units after a fault. It focuses on hardware-level re-synchronization of processing units. This patent was a primary reference in the IPRs against US7502958.
Potential Anticipation (35 U.S.C. § 102):
- This patent, in combination with others, was used to find claims of US7502958 unpatentable under obviousness (35 U.S.C. § 103) in IPR2023-01373 and IPR2024-00823. However, anticipation under § 102 requires direct disclosure of every element in a single reference. While it discloses redundant processing units and re-synchronization, it does not explicitly detail the firmware's role in coordinating with an operating system to idle and re-recognize processors, nor the specific determination of recoverability based on lockstep mismatch, as found in US7502958's independent claims.
- Therefore, US6862703B1 does not anticipate Claims 1, 13, 19, or 23 of US7502958 due to the absence of explicit OS interaction for processor management during lockstep recovery.

4. US 6,108,793 A (Kuppulusamy et al.)

Full Citation: US 6,108,793 A, "Method and apparatus for providing a fault-tolerant multiprocessing system," issued August 22, 2000.
Assignee: Sun Microsystems, Inc.
Priority Date: September 19, 1996.
Publication Date: August 22, 2000.
Brief Description: This patent describes a fault-tolerant multiprocessing system that can detect and recover from processor faults, including features for dynamic reconfiguration of processors. It was also a primary reference in the IPRs against US7502958.
Potential Anticipation (35 U.S.C. § 102):
- Similar to US6862703B1, this patent was heavily relied upon for obviousness arguments against US7502958. While it addresses fault tolerance and recovery in multiprocessing systems, it does not appear to explicitly disclose the specific firmware-OS interaction for idling and reintroducing lockstep processors, nor the firmware's determination of recoverability based on lockstep mismatch.
- Therefore, US6108793A does not anticipate Claims 1, 13, 19, or 23 of US7502958 for similar reasons as US6862703B1.

5. US 6,560,733 B1 (Chen et al.)

Full Citation: US 6,560,733 B1, "Method and apparatus for processor hot swap with operating system (OS) assistance," issued May 6, 2003.
Assignee: Intel Corporation
Priority Date: September 29, 2000.
Publication Date: May 6, 2003.
Brief Description: This patent describes a method and apparatus for hot-swapping a processor in a multiprocessor system with assistance from the operating system (OS). It involves the OS preparing for the removal of a processor and then accepting a new or replaced processor. This patent was used in some IPRs against US7502958.
Potential Anticipation (35 U.S.C. § 102):
- This patent is highly relevant as it explicitly discusses OS assistance for processor management (hot swap), including OS preparation for removal and acceptance of new processors. This aligns with the "triggering an operating system to idle" and "triggering the operating system to recognize" aspects of US7502958's claims. However, US7502958 specifically claims this in the context of firmware recovering lockstep for lockstep pairs of processors and determining recoverability based on lockstep mismatch. A direct read of US6560733B1 would be needed to confirm if it explicitly covers all these combined elements within a single disclosure, particularly the lockstep aspects and firmware's specific role in determining recoverability for LOL.
- Based on the brief description, US6560733B1 potentially anticipates elements of Claims 1, 13, and 19 related to OS interaction for processor management. However, it's not immediately clear if it fully discloses the "loss of lockstep" detection, firmware's specific role in recovering lockstep, and determining recoverability based on lockstep mismatch for a pair of processors, which are central to US7502958. Further detailed analysis would be required to definitively confirm full anticipation.

Other Cited References (General Overview):

Many other cited patents in US7502958 generally relate to fault-tolerant systems, redundant processors, error detection, and recovery mechanisms, but do not appear to explicitly combine all the specific elements of firmware-driven, OS-coordinated lockstep recovery as claimed in US7502958. These often focus on hardware-level redundancy, general fault handling, or different aspects of multiprocessor management without the precise firmware-OS interface for lockstep recovery.

Early Redundant Processor Patents (e.g., US4358823A, US5226152A, US5249188A, etc.): These patents generally describe dual or redundant processor systems for fault tolerance, including comparing outputs. However, they typically lack the sophisticated firmware-OS interaction for recovery as claimed in US7502958, especially the use of standard OS interfaces like ACPI for idling and re-recognition. They establish the foundational concept of lockstep.
Error Detection and Correction (ECC/Parity) Patents: Several citations relate to error detection and correction within memory or data paths. While US7502958 mentions these as part of error detection leading to LOL, the claims focus on the recovery method rather than the specific error detection mechanism itself.
Hot Spare Patents: While the concept of hot spares is old, US7502958's Claim 23 specifically describes firmware establishing a hot spare for a system boot processor and copying state in response to LOL, with a fallback to the OS-coordinated recovery for non-boot processors. A full anticipation would require a single prior art reference to disclose this entire conditional logic and firmware orchestration for boot processor hot spare in the context of lockstep.

In conclusion, while the cited prior art collectively demonstrates a rich landscape of fault-tolerant computing, redundant processors, and processor management techniques, a definitive anticipation (35 U.S.C. § 102) of all elements of US7502958's independent claims in a single reference is not immediately apparent from their titles, abstracts, or the brief descriptions provided within the US7502958 patent. The most promising candidate for closer examination regarding OS-firmware interaction is US6560733B1, but its complete disclosure of the lockstep-specific aspects of US7502958's claims would need a detailed review of its full text. The IPR proceedings already established obviousness (35 U.S.C. § 103) over combinations of these references, which is a different and lower standard than anticipation.