Obviousness

Obviousness Analysis of US Patent 10042116 under 35 U.S.C. § 103

This analysis identifies combinations of prior art references cited within US Patent 10042116 that would render its independent claims obvious to a person having ordinary skill in the art (PHOSITA). The primary motivation for combining these references stems from the well-known desire in the optical communications field to reduce insertion loss, minimize package size, and improve optical efficiency in transceiver modules.

Independent Claim 1: Arrayed Waveguide Grating (AWG) Chip

Claim 1 describes an AWG chip comprising:

1. A first end for coupling to an optical coupling receptacle to receive an optical signal with channel wavelengths.
2. A substrate.
3. A planar lightwave circuit (PLC) on the substrate, coupled to the first end, configured to demultiplex channel wavelengths.
4. A plurality of output waveguides coupled to the PLC, guiding light along a first light path towards a second end of the AWG chip.
5. A tapered region at the second end configured to receive and reflect light towards an exposed output interface region, wherein the exposed output interface region emits the received light from the AWG chip on the same side as the substrate without passing the received light through the substrate.

Prior Art Combination and Rationale:

A combination of US5617234A (Nippon Telegraph & Telephone Corporation) and US7376308B2 (National Research Council Of Canada) would render Claim 1 obvious.

• US5617234A teaches a multiwavelength simultaneous monitoring circuit employing an arrayed-waveguide grating (AWG), which inherently includes the elements of a first end for optical coupling, a PLC configured to demultiplex channel wavelengths, and a plurality of output waveguides guiding the demultiplexed light (as shown in FIG. 1, elements 11, 12, 13, and 15). AWGs are typically fabricated on a substrate as part of planar lightwave circuit technology.
• US7376308B2 specifically addresses "Optical off-chip interconnects in multichannel planar waveguide devices." This patent discloses an optical interconnect for diverting light out of an integrated circuit chip, such as a planar waveguide, to an off-chip photodetector array. The interconnect includes a "light-redirecting element" formed by an "angled facet" (micromirror) that reflects light out of the chip "towards an off-chip photodetector" (Abstract,,). Figure 4 of US7376308B2 clearly illustrates a planar lightguide array (analogous to output waveguides) with an angled facet (410) redirecting light (415) to an off-chip photodetector (420) located adjacent to a sidewall of the chip. The description further states that the redirected light "exits the chip 400 through the sidewall". This configuration of light exiting through a "sidewall" as depicted in Figure 4, which is effectively the exposed bottom surface of the waveguide core layer, directly anticipates or renders obvious the '116 patent's critical limitation of an "exposed output interface region" that emits light "on the same side as the substrate without passing the received light through the substrate" (by removing a portion of the substrate as described in the '116 patent at FIG. 5A and accompanying text).

Motivation to Combine:
A PHOSITA designing an optical demultiplexer would be motivated to minimize optical losses and device footprint, as explicitly noted as challenges in the background section of US10042116. Conventional AWG devices using fiber arrays for output coupling introduce significant insertion loss (1.0 to 2.0 dB) and increase the overall device length. US7376308B2 offers a direct solution to these problems by teaching a mechanism for direct off-chip coupling from planar waveguides to detectors without intermediate fibers, using an internal angled reflection. Therefore, a PHOSITA would find it obvious to integrate the direct off-chip coupling mechanism of US7376308B2 with the demultiplexing functionality of an AWG device taught by US5617234A to achieve a more compact and efficient AWG chip with reduced insertion loss.

Independent Claim 12: Optical Transceiver Module

Claim 12 describes an optical transceiver module comprising:

1. A transceiver housing.
2. A multi-channel receiver optical sub-assembly (ROSA) located in the housing, including an AWG chip (as in Claim 1, but with an added feature that the first end for coupling to the optical receptacle includes an angled surface to reduce back reflections).
3. An array of detector devices disposed adjacent to the output interface region of the AWG chip.
4. A multi-channel transmitter optical assembly (TOSA) including at least one laser package in the housing for transmitting optical signals.

Prior Art Combination and Rationale:

A combination of US7941053B2 (Emcore Corporation), US5617234A (Nippon Telegraph & Telephone Corporation), US7376308B2 (National Research Council Of Canada), and US7162124B1 (Luxtera, Inc.) would render Claim 12 obvious.

• US7941053B2 discloses an optical transceiver for 40 gigabit/second transmission, which includes both a TOSA and a ROSA within a transceiver housing (e.g., FIG. 1, TOSA 102 and ROSA 104). This reference establishes the overall transceiver module structure. Other patents like US8831433B2 (Applied Optoelectronics, Inc.) further reinforce the concept of multi-channel TOSAs within transceiver modules.
• The AWG chip within the ROSA (elements 1, 2, 3, 4, and 5 of Claim 1, including the direct coupling mechanism) would be rendered obvious by the combination of US5617234A and US7376308B2, as detailed for Claim 1 above.
• The feature of the "first end for coupling to the optical coupling receptacle includes an angled surface to reduce back reflections" is a known optical design technique. US7162124B1 explicitly mentions using "an angle polished facet on the end of the fiber to reduce back reflections" in the context of a fiber-to-chip coupler. Applying this established technique to the input end of an AWG chip to improve coupling efficiency and reduce back reflection would be an obvious design choice for a PHOSITA.
• The "array of detector devices disposed adjacent to the output interface region of the AWG chip" is directly taught by US7376308B2, which shows off-chip photodetectors (420) placed adjacent to the sidewall where light is redirected from the planar waveguide.

Motivation to Combine:
A PHOSITA designing an optical transceiver module (as generally taught by US7941053B2) would constantly seek ways to improve performance, reduce size, and lower cost, as these are inherent goals in the industry. The '116 patent's background explicitly states these challenges. Recognizing the significant insertion losses and space constraints associated with fiber array coupling in the ROSA, a PHOSITA would be motivated to adopt direct coupling techniques. US7376308B2 provides a clear teaching for direct off-chip coupling from planar waveguides to detectors via angled facets and sidewall emission, directly addressing these problems. Incorporating an AWG (from US5617234A) as the planar waveguide device for demultiplexing, and further incorporating the known technique of an angled input surface for back-reflection reduction (from US7162124B1 or general optical knowledge), into a standard transceiver module (from US7941053B2) would be an obvious design choice. This combination achieves the desired improvements in optical efficiency and compactness without requiring inventive leaps.